The USC IP block enables the infrastructure to communicate with a debug host or other external resource via a broad range of interfaces. A two-pin port provides an enhanced SWD-style (serial wire debug) interface which is particularly useful for severely pin-limited SoCs. This is electrically compatible to standard SWD, meaning it can use the same connectors and probes.
For less tightly-constrained designs, a three-wire option allows faster full-duplex communication using the same protocols, and a number of other serial modes. A high-speed link that supports Aurora and other SerDes-based connections serves applications that need to move high volumes of debug data very quickly – or chip designs in which SerDes are the only available interfaces. All of these use UltraSoC’s rich XML-based message procotocol, which is supported by a variety of development and analytic tools.
“We have created a vendor-independent universal SoC debug, performance monitoring and analytics platform,” says Rupert Baines, UltraSoC CEO. “We have an extensive library of modules, giving SoC development teams the flexibility to choose the best tools to address their needs: anywhere on an SoC, across all IP, from all vendors. The core of our offering is the ability to intelligently monitor any on-chip activity and distinguish the critical information, making development more efficient. Having the results easily available over a variety of interfaces is a key strand in our successful strategy to help customers accelerate SoC development, cut costs and eliminate bugs.”
UltraSoC says its vendor-independent technology allows engineering teams to understand what is really happening inside their SoCs, non-intrusively and at wirespeed. According to the company this results in accelerated time-to-market, easier detection of bugs, improved performance and reduced power consumption. Serving the trend towards SoCs that combine multiple processors with custom logic developed in-house, UltraSoC’s silicon IP can control and monitor the behavior of any on-chip structure, including leading third-party cores from ARM, CEVA and Cadence/Tensilica. The technology interworks gracefully with proprietary debug systems such as ARM’s CoreSight, and can integrate with emerging network-on-chip (NoC) architectures such as those from Sonics, Arteris and NetSpeed.
Versatile communications is an established strength of the UltraSoC architecture: these new interface options extend the range of communicators in the UltraSoC portfolio that already includes USB, JTAG, memory-write and others. The company recently launched a unique, patented technology that allows a single high-speed on-chip interface to be used simultaneously for both system communication and for analytics applications such as debugging. This allows existing interfaces on the SoC – for example USB, Ethernet or PCIe – to be used for development, eliminating the need for debug-specific interfaces. The new USC component complements that range, providing more off-chip communications possibilities. Alternatively, the UltraSoC fabric can connect to an on-chip processor or memory, allowing it to operate “autonomously” in the field as well as in a development lab.