Chips are going vertical with finfets and TSV, says Cadence vice-president
Looking back on 2013, writes Nimish Modi is Cadence’s senior vice-president, marketing & business development, we might say it was the “vertical” year. Consider:
- FinFETs emerged from foundries as test chips to help the industry keep up with Moore’s Law
- 3D-IC solutions with silicon interposer and through-silicon via (TSV) technologies matured to help performance, reduce power in lower small factors for multi-die configurations
- System companies continued their trend of vertical aggregation.
Add to these major 2013 highlights a fourth, which in many ways was crucial in enabling the first three: Companies across the board increased their use of IP and need for quality, time-to-market requirements as vendors delivered more integration-ready IP and IP subsystems.
Let’s examine these, one by one and then consider what’s driving all this:
3D ICs promise “more than Moore” integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs. While these engineering efforts were years in the making, they culminated in 2013.
In January, a 14nm test chip was taped out in a collaboration involving Cadence, ARM and Samsung. In the springtime, Cadence, ARM and TSMC joined hands to tape out an ARM Cortex-A57 device as 16nm. Two months later, UMC taped out a 14nm FinFET device.
3D ICs with TSV
Performance and area real estate have been driving the vertical dimension for several years now. And 3D IC packages pack heterogenous die—logic, memory, RF, MEMs—at different process nodes to create different solutions. Micron is bullish on its Hybrid Memory Cube technology. SK Hynix, Fujitsu, Samsung and others are said to have technologies in the works.
From a design standpoint, extensive retooling is not needed for 3D ICs, although EDA vendors are developing new capabilities for the design flow ranging from early floor planning to place and route to test.
Verticalization of System Companies
Application-driven system design is clearly where the industry is headed. Companies such as Google, Apple, Facebook and Amazon are hiring enormous teams of engineers, when just a few years ago they were buying what amounted to off-the-shelf electronics to serve their system needs.
They’re designing their own system architectures because their business, storage, networking and power-management needs are so unique that that’s the most cost-effective path for them.
And that also leads to the fourth interesting trend of 2013: The maturation of integration-ready IP ecosystem.
Engineering teams can no longer focus just on components of a larger design. This approach creates seams in the larger design, and where these seams come together, disaster can fester.
We’re delivering a growing portfolio of integration-ready IP as well as complete flows to minimise those seams and discontinuities. Yes, you still need simulation but you also need to emulate the whole system together, and you need a methodology that embraces hardware and software design together from project start.
In fact, system verification–including hardware-software integration–is the longest pole in the tent with respect to system time-to-market.
What’s driving these trends?
Clearly it’s the mobile revolution and the evolution of the network. With the number of mobile devices surpassing the number of humans on the planet and the amount of mobile data soaring toward 1 exabyte/month, the network as we’ve known it is changing.
It’s, as I mentioned earlier, changing the way systems companies engineer and create value–fine tuning/optimisation across the stack thereby providing unique differentiation & faster innovation; and it’s influencing how IP providers and EDA vendors deliver trusted and integration-ready so their customers get to market faster.