Mentor Graphics roadmap for big chip emulation
The deployment of hardware emulation has evolved rapidly in the past five years, and the market has grown in response to recent innovations, many of which are driven by the Mentor Graphics Veloce product group. Perhaps the most significant evolution for emulation is its transition from the engineering lab to the datacenter.
As little as five years ago most hardware emulators sat in an engineering lab, hard-wired to multiple, physical, speed adaptors used to replicate the end environment of the chip being verified. These days, when I tour our customers’ facilities, they take me to the datacenter to see their Veloce emulators, not the engineering lab.
My team at Mentor Graphics, driven by demand from our most advanced users, pioneered the move to the virtual lab, where peripheral devices such as PCIe, USB, Ethernet, and multimedia exist in virtual space and don’t require specialised hardware or a maze of I/O cables. Virtual peripherals permit instant reconfiguration of the emulator for any design or project team and access by more users, maximising utilisation of Veloce emulators and boosting the customer’s return on investment.
Owing to their lack of flexibility, physical peripherals often lead to underutilization of the emulator. Unique designs demand a unique set of peripherals, and each simultaneous user requires their own peripheral suite, effectively personalizing the emulator to a single project and limiting the number of users.
The emulator often sits idle on nights and weekends, since the set of unique physical peripherals effectively locks out other project teams around the world who otherwise could make productive use of the resource during off hours. Veloce’s virtual peripherals are instantly configured from any place around the globe, resulting in high utilisation of this capital investment.
Our focus on full SoC software execution and debug also drives growth of the emulation market. Comprehensive end-to-end validation of SW drivers pushing data out peripheral interfaces to target virtual peripherals greatly increases the verification coverage of advanced SoC software and hardware.
Our drive to make Veloce a productive, user-friendly tool for embedded SW developers has been well rewarded. Veloce is employed throughout the entire mobile device verification flow: from embedded processor and graphics IP suppliers, to mobile chip developers, to mobile phone and tablet engineering teams.
These customers demand a comprehensive hardware-software validation flow and are the reason I’ve directed substantial growth in our emulation-based SW debug tools group. The market segment may still be labeled “hardware emulation,” but embedded SW validation and debug is the real growth-engine driving our business. Customers who required two Veloce systems for HW validation now employ 16 to verify software and hardware together.
Clearly the growth in chip size and gate count has driven demand for more hardware emulation capacity. However, the boost in productivity made possible by virtual peripherals and the exploding demand for early SW-HW verification and debug are the primary reasons Veloce emulators are popping up in datacenters around the globe.
This is the most exciting time of my 14 years in hardware emulation. Closely monitoring my customers’ needs and devising ground-breaking technology to satisfy them has propelled Veloce and Mentor Graphics to record-high emulation sales, and I’ll continue to apply this proven strategy to the looming challenges facing all of us in the electronic design industry.
Author is Eric Selosse, vice president and general manager, Mentor Graphics Emulation Division.