Xilinx and Pico Computing provide Hybrid Memory Cube interface for 20nm FPGAs.

Xilinx, and Pico Computing have made available now a 15Gb/s Hybrid Memory Cube (HMC) interface for All Programmable UltraScale devices.

The Xilinx UltraScale devices support the HMC bandwidth of 4 lanes, comprised of 64 transceivers running up to 15Gb/s.

Pico Computing’s HMC controller IP offers high memory bandwidth.

“Customers can now leverage the industry’s only shipping 20nm FPGAs along with a validated IP core to bring their 15Gb/s HMC designs to market today,” says Xilinx’s Tamara Schmitz, “UltraScale FPGAs are the only devices currently available that can support all four HMC lanes to enable full memory bandwidth with additional transceivers for datapath and control signals.”

Tags: memory bandwidth, Pico Computing, Xilinx, Xilinx UltraScale

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