CEA-Leti believes FD-SOI chips work better under pressure

French research centre CEA-Leti believes it has developed a semiconductor process technology technique which will produce faster ICs using FD-SOI (fully-depleted silicon on insulator) processes.

The Grenoble-based centre has developed two techniques to induce local strain in FD-SOI processes and it believes the result will be faster chips with no power penalty.

The techniques apply compressive strain to silicon germanium (SiGe) die for PFETs and tensile strain to silicon die for NFETs.

The two techniques Leti developed can induce local stress as high as 1.6 GPa in the MOSFETs channel.

Maud Vinet

Maud Vinet

According to Maud Vinet, head of Leti’s Advanced CMOS Laboratory. “These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices, and further position the technology to be a vital part of the Internet of Things and electronics products of the future.”

The compressive  strain is transfered from a relaxed SiGe layer on top of SOI film. In a recent paper in the ECS Journal of Solid State Science and Technology, Leti researcher Sylvain Maitrejean described how with this technique he was able to boost the short-channel electron mobility by more than 20 percent compared to unstrained reference.

“This shows significant promise for enhancing the on-state currents of CMOS transistors and thus for improving the circuit’s speed,” said the paper.

For tensile strain, Leti researchers have shown that with this local-stress technique they can turn regular unstrained SOI structures into tensile strained Si (sSOI), for NFET areas.

The FD-SOI process also can also be applied to compressive strain creation, as presented at the 2015 Silicon Nanoelectronics Workshop (SNW) conference.

“Strained channels enable an increase in the on-state current of CMOS transistors. As a result, the corresponding IC circuits can deliver more speed at the same power, or reduced consumed power and longer battery life at the same performance,” said CEA-Leti.

The researchers also believe the same technique can be used to increase performance of n and p MOSFET transistors via mobility enhancement of electrons and holes. These kinds of techniques enable boosting of the carrier transport in the CMOS channels, and thus increasing the on-state currents.

Beginning with the 90nm node, this strain option has been one of the main approaches of the microelectronics industry for improving the IC speed in bulk transistors. While it was not necessary at the 28nm node for FD-SOI, it becomes mandatory beyond the 22/20nm node.

 

 

 


Leave a Reply

Your email address will not be published. Required fields are marked *

*