Dublin firm’s high speed ADC cuts power in 4G LTE design
The successive approximation register (SAR ) ADC is aimed at high speed wireless systems LTE and 802.11ac Wi-Fi.
The chip, which is fabbed on a 40nm process, has a power consumption of 6mW. According to the supplier, a move to a 28nm process will half this power consumption.
“As an industry we have a healthy obsession with high efficiency and small die area and we at S3 Group embrace this obsession by continuously innovating to address the incessant need for faster access to mobile content,” said Dermot Barry, v-p of the silicon business at S3 Group.
Darren Hobbs, director of product management at S3 Group has written in a blog, advice on choosing the high speed ADCs.
“The three key drivers that are pushing the evolution of data converter design are dynamic linearity over certain bandwidths, power consumption and silicon area,” said Hobbs.
“Presently, excellent dynamic linearity equivalent to greater than 10.2 ENOB is expected over bandwidths ranging from a few MHz to 80MHz, cellular LTE occupying the lower end, whilst WiFi’s 802.11ac occupies the higher-end. Typical power consumption budgets of less than 15mW are required, whilst silicon area utilization of the order of 0.15mm2 and below is permitted. These are certainly tough requirements and only getting tougher.”
As well as ADCs and DACs, S3 Group’s IP portfolio includes PLLs, analogue front-ends, power management and RF transceivers. Its silicon IP has been fabbed at TSMC, Globalfoundries, UMC, SMIC, IBM and Tower at nodes ranging from 180nm to 28nm.
Based in Dublin, the firm has development centres in Ireland, Poland, the Czech Republic and Portugal.