eSilicon's fast memory on TSMC's 28nm
eSilicon is offering memory compilers for TSMC’s 28nm and 40nm process technologies.
The semiconductor design and manufacturing services company’s eFlex and eFlexCAM embedded memory products include ternary content addressable memories (TCAMs) and multi-port register files.
High bandwidth parallel processing requires comparable memory processing speed. TCAMs search an entire memory database in one to two cycles.
eSilicon’s TCAMs can provide up to 1.6 billion search results in one second. Multi-port memories process multiple memory requests in parallel within a single clock cycle.
“We are now offering our third generation of eFlex and eFlexCAM embedded memory compilers on TSMC’s 28HPM process,” said Patrick Soheili, vice president and general manager of eSilicon’s IP Solutions Group.
The 28HPM TCAMs can provide performance of up to 1.6 billion searches per second (BSPS) under typical operating conditions and a latency of 1-2 clock cycles. TCAM performance is 800 million searches per second (MSPS) under worst operating conditions.
The TCAM compilers include features such as hardened priority encoders, multiple options to lower power, and column redundancy for higher yield.
TCAM IP includes multi-width search mode to switch dynamically between IPv4 and IPv6 searches. eSilicon also offers built-in self-test (BIST) and built-in self-repair (BISR) for higher test coverage during wafer sort and production.
eSilicon’s 28nm four-port register file can offer speeds approaching 2 GHz under typical operating conditions, while the 28nm asynchronous register file offers read speeds in excess of 2.5 GHz.
The four-port register file supports two independent read and two independent write ports, and plays a critical role in increasing system bandwidth by supporting parallel operations.
These memories provide zero clock latency overhead, deterministic timing (versus RTL/synthesis-based solutions) and easily integrate on chip with existing design flows. The asynchronous register file provides an independent write and an independent asynchronous read port. These memories enable fast access times for downstream operation.