Micron shrinks NAND with three bits per cell
The memory device uses a triple-level-cell (TLC) design which stores three bits of information per cell.
This means the device is more than 25% smaller than the same capacity of Micron’s 20nm multi-level-cell (MLC) NAND device.
Micron is sampling the 128Gb TLC NAND device and it will be in production in Q2.
“This is the industry’s smallest, highest-capacity NAND flash memory device,” said Glen Hawk, vice president of Micron’s NAND Solutions Group.
Micron is presenting a paper on the 128Gbit TLC NAND device at the upcoming International Solid-State Circuits Conference (ISSCC) on Feb. 19.Tags: flash, Micron, NAND