Spansion cuts pin-count in high speed NOR flash chips
Spansion has introduced a chip interface it claims will reduce the number of pins on large high performance system-on-chip (SoC) devices.
The first devices to be based on the HyperBus interface will be NOR flash memory with read throughput of up to 333Mbyte/s.
“This is more than five times the fastest Quad SPI flash currently available with one-third the number of pins of parallel NOR flash,” said Spansion.
The 12-pin HyperBus interface consists of an 8-pin address/data bus, a differential clock (2 signals), one “chip select” and a “read data strobe” for the controller, reducing the overall cost of the system.
The interface is implemented in the HyperFlash memory which initially includes three densities: 128Mbit, 256Mbit and 512Mbit with the 512Mbit devices sampling in the second quarter of 2014.
The memories will be available in a space-saving 8x6mm ball grid array (BGA) package.