UK start-up makes 28nm FD-SOI embedded memory “breakthrough”
SureCore, the UK-based embedded memory process developer, has announced that it has taped out its low power SRAM IP demonstrator chip in STMicroelectronics’ 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) process.
The device will be used to validate the benefits of the start-up’s patented array control and sensing scheme, which is claimed to lowers active power consumption to deliver greater than 50% power savings compared to current offerings in the same process.
The SRAM IP memory was designed through a combination of detailed analysis and the use of advanced statistical models.
“In post layout simulations the memory showed 75% less power for read cycles and 50% for write cycles. In addition, the technology promises improved leakage performance saving between 20% and 40% depending on operating corner,” said the company.
“This is a major milestone for the company – the demonstrator device will allow us to take the next steps commercially,” said Paul Wells, sureCore CEO.
Although it is implemented in an FD-SOI process, Wells says the technology is not process specific and will map to both bulk CMOS and FinFET technologies.
“We are currently working closely with partners to implement this in 40nm and 28nm bulk CMOS,” said Wells.
Gold Standard Simulations worked with sureCore and non-executive director and CEO of GSS, Professor Asen Asenov, observed, “Having worked closely with sureCore for over two years it is encouraging to see a fresh perspective. They have tapped into GSS’ expertise and modelling capabilities to really understand the challenges posed by variability. The novel circuitry developed both improves variability tolerance and lowers power consumption – key metrics for next generation SRAM solutions.”
According to Horacio Mendez, executive director of the SOI Industry Consortium: “sureCore is solving a critical problem for SoCs: power reduction for the memory components.”