ARM explains good interrupt control for low power processors
Effective interrupt control is achievable in low power microcontrollers, writes Joseph Yiu, embedded technology specialist at ARM
Interrupts are a major feature of most embedded microcontrollers and effective real time response to interrupts is vital in low power systems that often rely on a ‘run fast then stop’ approach to energy efficiency.
Where power consumption is important, as in battery operated devices, efficient, low latency, interrupt handling may also be required to wake the microcontroller from a sleep state where the program execution is suspended until required to do something by a peripheral event.
The ARM Cortex-M series processors each feature an integral nested vectored interrupt controller (NVIC) to provide interrupt handling capabilities.
In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors the NVIC supports up to 32 interrupt requests (IRQ), a non-maskable interrupt (NMI) and various system exceptions.
The Cortex-M3 and Cortex-M4 processors extend the NVIC to support up to 240 IRQs, 1 NMI and further system exceptions.
Most of the NVIC settings are programmable. The configuration registers are part of the memory map and can be accessed as C pointers. The Cortex Microcontroller Software Interface Standard (CMSIS) library also provides various helper functions to make interrupt control easier.
Inside the NVIC, each interrupt source is assigned an interrupt priority. A few of the system exceptions such as NMI have a fixed priority level and others have programmable priority levels. By assigning different priorities to each interrupt the NVIC can support Nested Interrupts automatically without any software intervention.
The architecture provides 8 bits of priority level settings for each programmable interrupt or exception. To reduce gate count only parts of these registers are implemented.
In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture), four programmable levels are provided. In the Cortex-M3 and Cortex-M4 processors (ARMv7-M architecture), the designs allows from eight priority levels to 256 levels.
To make the Cortex-M series processors easier to use they use a stack based exception model. When an exception takes place a number of registers are pushed on to the stack.
These registers are restored to their original values when the exception handler completes. This allows the exception handlers to be written as normal C functions and also avoids the hidden software overhead of interrupt processing.
In addition, the Cortex-M series processors use a vector table that contains the address of the function to be executed for each interrupt handler. On accepting an interrupt the processor fetches the address from the vector table. Again this avoids software overhead and reduces interrupt latency because there is no need to use software to branch to starting addresses of the handlers.
Various optimisation techniques are also used in the Cortex-M series processor implementations to make interrupt processing more efficiency and make the system more responsive:
Tail chaining – If another exception is pending when an Interrupt Service Routine (ISR) exits, the processor does not restore all saved registers from the stack and instead moves on to the next ISR. This reduces the latency when switching from one exception handler to another.
Stack pop pre-emption – If another exception occurs during the unstacking process of an exception, the processor abandons the stack Pop and services the new interrupt immediately as shown below.
By pre-empting and switching to the second interrupt without completing the state restore and save, the NVIC achieves lower latency in a deterministic manner.
Late arrival – If a higher priority interrupt arrives during the stacking of a lower priority interrupt, the processor fetches a new vector address and processes the higher priority interrupt first.
The ARM NVIC technology, with these optimisations, enables the interrupt overhead in low-power systems to be reduced as the interrupt loading increases.
This ensures high interrupt processing throughput the systems while maintaining the low power consumption these systems demand.
ARM NVIC and the Cortex processor architecture is available from http://infocenter.arm.com/help/index.jsp