EnSilica’s eSi-RISC soft processor cores are aimed at SoCs
Chip design firm EnSilica has introduced three configurable and soft processor cores for asics and FPGAs: eSi-1600, eSi-3200 and eSi-3250.
The cores are based on the EnSilica’s eSi-RISC scalable processor architecture, which supports both 16 and 32bit configurations; selectable Harvard/von Neumann memory; and configurable cache options.
“The highly pipelined nature of their design gives customers a solution that can be migrated between FPGA types or even to ASIC technologies,” said EnSilica.
eSi-1600 is a 8,500 gate 16bit processor that delivers up to 0.7Dmips/MHz.
Aimed at energy monitoring, intelligent sensors, medical use, and wireless networking, power is 15µW/MHz on 0.13µm silicon.
eSi-3200 is a 32-bit core designed for use with on-chip memory.
It has 15,000 gates, and the five-stage pipeline can run at 700MHz on a 90nm process.
At 0.9Dmips/MHz, the core is aimed at applications requiring more code space than the eSi-1600 can provide, such as wireless communications and media processing, said EnSilica.
eSi-3250 is optimised for off-chip memory and has configurable instruction and data caches (4-64kbyte, direct mapped or 2 or 4-way associative).
“In this configuration, the core is still only 20k gates,” claimed the firm.
It can deliver 1.2Dmips/MHz, and there is an optional IEEE 754 floating point unit and MMU.
Intended applications include those with complex operating systems.
All cores have an instruction set that has a number of optional instructions and addressing modes, as well as support for up to 96 user-defined instructions.
“System clocks speeds of over 200MHz can also be achieved in Altera Stratix IV and Xilinx Virtex-6 FPGAs,” said EnSilica. “All processors use the industry standard AMBA APB and AXI buses. We have a library of APB-based peripherals, including UART, SPI, I2C, Timers and a 10/100 Ethernet MAC.”
Development tools have been ported to the architecture to create a single development tool chain including GCC 4.4.0, Binutils 2.20 and GDB 7.0 – all integrated into the Eclipse 3.5 development environment.Tags: Asics, chip, cores, design, EnSilica, FPGAs, introduces, processor, three