PA Semi attacks performance/Watt

One of Silicon Valley’s most closely guarded secrets, the activities of start-up PA Semi, has finally been revealed after two years of “stealth” development.

The firm has unveiled a 64-bit multi-core processor family based around the Power architecture, which it has licensed from IBM.

PA Semi said its PWRficient processors will raise the performance per Watt metric by a factor of ten, compared to today’s processors.

“The next wave of microprocessor innovation is contingent on solving the problem of dramatically increased power consumption,” said Dan Dobberpuhl, cofounder, president, and CEO. “We had to start from scratch, rethinking every step, to achieve our breakthrough performance-per-watt design.”

The firm is claiming to achieve clock speeds of 2.5GHz per core, while a two core device running at 2GHz consumes just 5 to 13W, depending on the application running.

In order to improve latency in the system, PA Semi integrates the chipset functionality alongside the processor. So processor cores, memory, north/south bridge and I/O all appear in one die.

The first chip, the PA6T-1682M – the two core device – integrates two DDR2 memory controllers, 2Mbyte of level two cache, eight PCI Express controllers, two 10Gbit Ethernet controllers and four Gbit controllers.

Sampling of this first device is set for Q3 of next year. Single core and quad-core versions will follow in 2007, said the firm. An eight core chip will arrive in 2008.

PA Semi is one of the biggest start-ups with a 150-strong team of developers who have previously worked on designs such as the Itanium, Opteron and UltraSPARC. Dobberpuhl was lead designer of the DEC Alpha and StrongARM processors.

www.pasemi.com

Tags: Digital Signal Processors, dsp, microcontroller, microprocessor, parallel processing, vliw

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