Altera Cyclone V FPGAs meet 5Gbit/s PCIe 2.0 spec
Altera has said its 28nm Cyclone V GT FPGA product has completed compliance testing with the PCI Express (PCIe) 2.0 specification.
This means the Cyclone V GT FPGA supports PCIe 2.0 data rates of 5Gbit/s.
”The Cyclone V GT FPGA successfully passed all PCI-SIG compliance and interoperability tests at the most recent PCI-SIG workshop and is currently included on the PCI-SIG Integrators List,” said Altera.
Cyclone V FPGAs have 5Gbit/s transceivers and two hardened PCIe IP blocks embedded within the device.
Hard PCIe IP blocks
The PCIe 2.0-compliant hard IP blocks consists of the PHY/MAC, data link and transaction layers. The blocks can be configured to function as an end point or a root port and supports up to x4 lanes.
The devices also can be configuration via protocol using PCIe, which allows the hard PCIe core in the devices to operate without the FPGA fabric being loaded.
”This ensures the PCIe end point is ready for enumeration under the PCIe protocol’s required 100ms specification regardless of the configuration method being used,” said Altera.
Cyclone V GT FPGAs are currently in production.