Altera to launch 20nm FPGAs next year
Altera intends to launch 20nm products next year with volume production starting in 2014, Bradley Howe, senior vice president for R&D at Altera, told a meeting in London this morning.
The process will deliver twice the density of 28nm and a 60% reduction in static and dynamic power, said Howe. It will deliver 40Gbit/s transceiver and 28Gbit/s backplanes.
When it is architected for high performance, it will deliver 5TFLOPS DSPs, said Howe.
The 20nm process for which Altera’s products are being developed is TSMC’s bulk CMOS process. Howe said the TSMC’s 20nm SRAM is now yielding ‘extremely well’ .
In parallel, Altera is “actively working” on finfet design right now, said Howe. TSMC has said it will be producing a 20nm finfet process and Altera doesn’t rule out using it for a second generation of product.
Altera is also looking at FD-SOI as a possible way to go.
Asked if Altera is concerned about the fact that its much smaller competitors Achronix and Tabula are getting wafers from Intel, Howe said: “We’re concerned about any competition. Those two companies have fundamental issues and one of them is power. One has a high performance platform and, from what we see, the power is very much higher than the mainstream of the industry can tolerate.”
“They also have issues on the robustness of their design environments. Altera has as many people working on design software as we do on our silicon platform,” said Howe.