Microsemi sampling SmartFusion 2
Microsemi has engineering samples of its flash-based FPGAs, SmartFusion2, with first production scheduled for early next year.
Designated M2S050T the chips are aimed at advanced security, high reliability and low power applications in communications, defense & security, aerospace and industrial application.
The FPGAs integrate a 166MHz ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and communication interfaces.
“SmartFusion2 SoC FPGAs are designed for challenging safety-critical applications communications, defense & security, aerospace and industrial applications where it is essential for devices to operate reliably and flawlessly,” says Esam Elashmawi, vice president and general manager at Microsemi.
Microsemi says that customers plan to use the chips in flight data recorders, weapons systems, defibrillators, handheld radios, communications system management applications and industrial motor control.
Recent attacks on communications, defense & security, aerospace and industrial systems have highlighted the need for security and anti-tamper safeguards within electronic systems, says Microsemi, and SmartFusion2 includes security capabilities to protect designs against tampering, cloning, overbuilding, reverse engineering and counterfeiting with state-of-the-art design protection based on non-volatile flash technology.
The chips incorporate a root-of-trust device with secure key storage capability using what Microsemi claims to be the FPGA industry’s only physically unclonable function (PUF) key enrollment and regeneration capability.
The FPGA is protected from differential power analysis (DPA) attacks using technology from the Cryptographic Research Incorporated (CRI) portfolio.
Users may also leverage built-in cryptographic processing accelerators including: advanced encryption standard (AES) AES-256, secure hash algorithm (SHA) SHA-256, 384 bit elliptical curve cryptographic (ECC) engine and a non-deterministic random bit generator (NRBG).
The chips meet IEC 61508, DO254 and DO178B standards, and feature SEU immunity of zero failures in time (FIT). It does not require external configuration, which provides an added level of security since the SoC FPGA retains its configuration when powered off and enables device “instant-on” performance.
The FPGAs protect all its SoC embedded SRAM memories from SEU errors. This is accomplished through the use of single error correction, double error detection (SECDED) protection on embedded memories such as the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the DDR memory controllers.
The FPGAs offer designers 100x lower standby power compared to equivalent SRAM-based FPGAs without sacrificing performance. The FlashFreeze standby power mode can be initiated with a simple command. In this mode all registers and SRAM retain state, I/O state can be set, the microprocessor sub-system (MSS) can be operational while low frequency clock and I/Os associated with MSS peripherals can be operational. The device can enter and exit Flash*Freeze mode in approximately 100 micro seconds. This is ideal for low duty cycle applications where short bursts of activity are required, such as defense radio where size, weight and power are critical.
The chip has 10 mW of static power for 50K LUT (look-up table) device, including the processor and without sacrificing performance. With the Flash*Freeze standby mode, power drops to 1mW. This is about 100 times lower standby power than similar SoC FPGAs or FPGAs, says Microsemi.
The ICs are available with a range of density from 5K LUT to 120K LUT plus embedded memory and multiple accumulate blocks for digital signal processing (DSP). High bandwidth interfaces include PCI Express (PCIe) with flexible 5G SERDES along with high-speed double data rate DDR2/DDR3 memory controllers.
The device also includes a microprocessor sub-system (MSS) with a 166 MHz ARM Cortex-M3 processor, on chip 64KB eSRAM and 512KB eNVM to minimize total system cost. The MSS is enhanced with an embedded trace macrocell (ETM), 8 Kbyte instruction cache, and peripherals including controller area network (CAN), Gigabit Ethernet and high speed USB 2.0. Optional security accelerators can be used for data security applications.
System designers can use the Libero SoC software toolset. Libero SoC integrates synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and push button design flow.
Firmware development is integrated in Libero SoC with compile and debug available from GNU, IAR and Keil, and all device drivers and peripheral initialization is auto generated based on System Builder selections.
The ARM Cortex-M3 processor includes operating system support for embedded Linux from EmCraft Systems, FreeRTOS, SAFERTOS and uc/OS-III from Micrium.