Through-silicon via technology revolutionises chips
Through-silicon via (TSV) on chip interconnection of memory, processor and sensor elements looks the most likely route for 3D chip design, writes Richard Wilson
As the complexity of system-on-chip semiconductor devices grows designers are exploring the practicality of so-called 3D chips.
3D chips can take many forms but the most practical would seem to be through-silicon via (TSV) technology which allows die to be stacked on top of one another.
A common element of all processor-based systems is memory and Samsung Electronics and Micron Technology are proposing an open interface specification for TSV-based memory technology called the Hybrid Memory Cube (HMC).
Details of HMC technology are vague, but it uses a stack of TSV-bonded DRAM die with the potential for higher memory density and data paths.
The companies claim a x15 improvement in density over traditional DDR3 DRAM devices.
“This collaborative is an accelerator for highly promising technology that will benefit the entire industry,” said Jim Elliott, v-p memory marketing at Samsung Semiconductor.
“HMC is unlike anything currently on the radar,” said Robert Feurle, Micron’s v-p for DRAM marketing.
Samsung has already demonstrated how TSVs and 3D packaging can reduce power consumption in 32Gbyte DDR3 registered DIMMs.
“TSV allows us to stack dies onto one another and therefore increase the density of any given package,” Samsung spokeswoman Ujeong Jahnke told Electronics Weekly. “The RDIMM is manufactured by stacking 4Gbit DRAM die.”
The module consumes 4.5W, claims Samsung: “Compared to the 30nm-class 32Gbyte load-reduced DIMM, which offers advantages in constructing 32Gbyte or higher memory solutions, the 32Gbyte RDIMM module provides approximately 30% energy savings.”
For the TSV system processor you can use an FPGA. FPGA firms Altera and Xilinx also support the TSV memory interface specification.
Xilinx has described a multi-die Virtex-7 design with up to four FPGA slices configured side-by-side with interconnection provided by a silicon interconnect die stacked beneath the FPGA slices.
“The aim is to remove the need for chip-to-chip interconnections in the highest density FPGAs, with two million logic cells, which can limit signal bandwith and add to power consumption,” said the FPGA company.
With the FPGA slices stacked onto of the silicon interconnection layer TSVs are used for the chip connections.
The stacked silicon interconnect structure means that data flows between the adjacent FPGA die through fixed data paths in the silicon interconnect layer.
The company also claims that be sitting multiple die side-by-side rather than stacked on top of each other will improve thermal management.
The TSVs replace on-chip bond wiring with short vertical interconnects in multi-chip MEMS devices, such as smart sensors and multi-axis inertial modules.
ST already has its TSV technology in full production MEMS devices.
“There is a great demand for smaller packages in the consumer market. This implementation of TSV in MEMS devices opens a path to reduced footprints and increased functionality in mobile phones and other gadgets,” said Benedetto Vigna, general manager of ST’s analogue, MEMS and sensor group.Tags: Altera, chips, dram, FPGAs, Samsung, ST, TSV, Xilinx