TierLogic Launches 3D FPGAs


Today, TierLogic breaks out of its seven years in Stealth Mode to launch its 3D FPGAs. The company is open for business now, and is offering free NREs to early adopters.

TierLogic’s approach is to make a monolithic chip which can act both as an FPGA and an ASIC.

“It’s the first monolithic 3D FPGA – an FPGA and ASIC in a single die”, says TierLogic’s Paul Hollingworth.

The primary claim for TierLogic’s approach is that it provides either an FPGA, or an ASIC, or a seamless, inexpensive and fast FPGA-ASIC conversion.

When acting as an FPGA, TierLogic calls its chip TierFPGA; when acting as an ASIC, it is called TierASIC.

Another claim for the technology is that TierFPGA is half the cost of high-end FPGAs, and 20% lower than low-end FPGAs; and the TierASIC cost is 50% lower than conventional ASIC with an NRE of under $25,000.

And a further claim is that, because TierLogic uses Mentor synthesis, no new learning is required for FPGA designers and that users design only once – there is no redesign required for ASIC. The functionality and the timing for the TierFPGA and the TierASIC are identical. The same tool-chain produces both FPGAs and ASICs. The customer designs once, and gets the benefit of two implementations.

“Zero customer effort, no risk, and a four week turn around time for converting a TierFPGA into a TierASIC because TierLogic holds wafers held at Metal 8 – and only one layer has to be changed,” says Hollingworth.


The TierLogic chip uses nine layers of metal which hold the core logic array, over which the configuration SRAM transistors are e held in an amorphous silicon TFT layer on top of the metal layers. The TFT layer is currently made using 0.18 micron technology and is scalable.

“Metal 9 is the layer that is changed”, says Hollingworth, “all we use the TFT for is to store a static 1 or 0 as a latch.”

By moving the configuration SRAM to TFT-based SRAM, TierLogic achieves a much more efficient FPGA. The FPGA design is turned into an ASIC by replacing the TFT SRAM with metal. So there’s no difference between TierFPGA and TierASIC up to Metal 8.

The fabrication is standard CMOS. The customer gets an ASIC using FPGA tools and with the benefit of FPGA prototypes. So the risk of ASIC is removed, the cost of FPGA is reduced and the time and cost of the FPGA-ASIC conversion are substantially reduced.

The resulting TierASIC – without the TFT layer – is significantly cheaper to manufacture. The yield is higher in the base layers. Users only need to test those transistors actually used in the design and can use ASIC test methodology.

“It’s not the densest standard cell because it has switching elements”, says Hollingworth, “but it’s significantly cheaper to manufacture.”

The silicon benefits are: lower power because the SRAM configuration has gone; higher security and reliability, and the use of the same silicon for FPGA and ASIC.

Asked if the TFT approach affected performance, Hollingworth replies: “In terms of slowing it down, it doesn’t at all. If it had changed the performance in any way, I wouldn’t have joined. The TFT layer doesn’t hold any of the timing paths. The top layer is just a series of switches.”

Asked if the configuration layer added to cost, Hollingworth replies: “TFT adds about 25% to the wafer cost – that will come down over time.”

TierLogic’s long period in Stealth Mode – the company was founded in 2003 – was due to the need to invent a process technology.

“Since 2003 we’ve been, filing patents and working on process technology”, says Hollingworth, “we’ve 50 patents granted and 20 pending. There are some wide patents, e.g. ‘Any kind of 3D structure connected with programmable circuits’. The patents cover new forms of transistor. We had to design a process technology, not just a chip. No one has done majority carrier devices in TFTs before.”

The company has 50 people in Santa Clara. 25 in Sri Lanka. The founding team comprises: CEO – Doug Laird who was a founder of Transmeta; CTO is Raminda Madurawe an ex-Altera guy with 97 patents; another founder, Peter Suaris, was chief scientist at Mentor and Tim Garverick, founder of Stretch and Adaptive Systems.

TierLogic’s market proposition is its TierFPGA has a much smaller die-size with a price about half that of conventional FPGA. No external configuration ROM is needed, there’s instant-on with no power-up configuration sequence, no configuration bitstream security risk and no configuration memory soft-error risk.

The pitch is that this approach provides: a zero-risk, zero effort conversion; very low NRE to go from TierFPGA to TierASIC; production TierASIC units four weeks after FPGA design freeze; no ASIC tools to purchase or learn; and you save 3-6 months compared to other FPGA-ASIC conversion flows.

Asked why a new approach to FPGA is needed, Hollingworth replies: “Scaling is only going so far and it will be so expensive – ruinously expensive particularly for small companies. The cost of leading edge technology 28nm design is $50m. We don’t think that’s necessary. If you can offer the same density as the technology two nodes earlier on the process curve, why don’t you?”

That explains the 3D approach: “Building skyscrapers is a good use of land because building materials are cheap.”

Another reason is pricing: “A lot of non-top-tier companies are not getting good pricing from the big boys,” says Hollingworth.

Innovation in the FPGA business has been lacking. “There hasn’t been much innovation in the last couple of decades, 3D FPGAs are now changing that”, says Hollingworth, “the programmable companies have driven down Moore’s Law but they haven’t innovated.”

For FPGA design, TierLogic uses Mentor synthesis. “We use Mentor synthesis so the TierLogic FPGAs look just like anybody else’s FPGAs”, says Hollingworth, “we don’t want customers to need to change thei r methodology.”

Tools were released in December and are being used by customers. Early adopters can register at TierLogic.

The first product will be TierASIC 90nm with the equivalent logic density of a 40nm FPGA. The first chips were received in September 2009. All circuit blocks were functional and TierASIC qualification was started.

The company intends to sample TierFPGAs in Q2. The first TierFPGAs were received at the end of December 2009. They proved integration with bulk CMOS and that TFTs will drive base-layers. TierLogic is starting running base wafers in Q1 to deliver samples.

“Today we can take someone else’s FPGA and convert it into a TierASIC,” says Hollingworth, “for that there is no NRE for early adopters with orders of $50,000+. TierLogic compiles the RTL, tapes out TierASIC devices and delivers samples. TierLogic does the work, funds the NRE and can deliver a pin-compatible device.”

So TierASICs can be made fully compatible and, for $100,000+ orders, free pin-compatible development is offered.

In the next phase, in Q2 2010, TierLogic will be shipping TierFPGAs and will be able to take an existing FPGA and turn it into a TierFPGA for prototyping and production and then converting it to TierASIC. “A seamless, zero-risk and zero-effort conversion,” says Hollingworth.

Following production qualified devices in Q4 this year, Phase 3 delivers prototype and production TierFPGAs, and volume production of TierASIC.

TierFPGAs will be able to be used for both prototyping and production, and TierASIC will be able to be used for volume production once the design is stable.

“We’re looking for early adopter customers to prove the concept by doing conversions of existing production FPGAs”, says Hollingworth, “we will install the tool on customers’ sites, help convert designs and provide ASIC samples – all free to early access customers.”

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