TSMC applies fine-pitch bump packages to Altera 20nm FPGAs

arria TSMC’s patented, fine-pitch copper bump-based packaging technology is being used in Altera’s 20nm Arria 10 FPGAs and system-on-chips (SoCs).

“Leveraging this technology helps us address the packaging challenges at the 20nm node,” said Bill Mazotti, vice president of worldwide operations and engineering at Altera.

Altera is shipping Arria 10 FPGAs based on TSMC 20SoC process technology.

TSMC’s fine-pitch copper bump technology is able to accommodate very high bump counts as required by high-end FPGAs.

“TSMC’s copper bump-based package technology provides excellent value for small bump pitch (<150µm) advanced silicon products featuring ELK (Extra Low-K) layers,” said David Keller, senior vice president, business management, TSMC North America.

Tags: Altera, packaging technology, technology, TSMC

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