Tool debugs JESD204B links from fast ADCs
Called the JESD204B Xilinx Transceiver Debug Tool, it includes software and HDL code and supports 312.5Mbit/s to 12.5Gbit/s serial data from Xilinx 7 series and Zynq-7000 FPGAs.
“The tool provides on-chip eye-scanning that augments the test and measurement process by statistically determining signal integrity inside the FPGA,” said Xilinx product manager Revathi Narayanan. “Where other techniques probe the outside of the FPGA package and acquire the signal before it’s been processed by Xilinx’s automatic gain control and equaliser blocks, ADI’s approach yields a more accurate result by utilising the Xilinx transceiver on-chip eye-scan feature to allow developers to monitor signal integrity and design margin inside the FPGA.”
The reference design gathers data from the on-chip Rx margin analysis feature in the 7 series IBERT core and manages the data locally inside the FPGA or on one of ARM Cortex-A9 cores, displaying data on an HDMI monitor or over Ethernet to a remote monitoring station.
“This use of “live” data enables signal fidelity to be monitored even after the design has been deployed in the field, which allows for real-time and predictive maintenance over the life of the product,” claimed ADI, which expects applications to include radar arrays and software-defined radio.