Xilinx: finfets deliver 56G PAM4 transceiver

Xilinx, has developed 16nm finfet-based 56G transceiver technology using the 4-level pulse amplitude modulation (PAM4).

“PAM4 solutions will help drive the next wave of Ethernet deployment for optical and copper interconnects by doubling bandwidth on the existing infrastructure,” said the firm. The company’s 56G PAM4 transceiver technology has been developed to tackle physical limitations of  data transmission at such line rates, including insertion loss and crosstalk.

56G PAM4It supports copper and optical interconnects for chip-to-chip, module, direct attach cable, or backplane applications and, said the firm, will enable next generation system designs for beyond terabit line cards, 400G to terabit chassis backplane.

The company teamed with TSMC to ready its PAM4 device for TSMC’s 16nm FinFET+ process. The transceiver is being built as part of a programmable device.

It will be demonstrated at the OFC show in Anaheim, California (March 22-24).

The IEEE LAN standard committee has prepared a paper on PAM4 modulation.

See also: Zynq UltraScale+ gets Micrium RTOS for all processors

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