EDA and IP

Lauterbach tool provides proof of timing data

Lauterbach says its TRACE32 tools can now offer proof of timing and code performance in real-time embedded systems.

This is possible because the tool can now export task event based trace data for external timing analysis. This can be used to trouble shoot and detect complex errors that only…

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3D PCB printer does pick-n-place too

New York-based start-up BotFactory is developing a rapid prototyping machine that prints PCBs and then picks-and-places components.

Called Squink and the subject of a KickStarter funding drive, “it sits on your desk, and prints and assembles your circuits in a matter of minutes on flexible or…

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CadSoft launches v7 of Eagle PCB

CadSoft has rolled its Eagle PCB layout tool to version 7, improving the auto-router and allowing large designs to be split across a team.

The auto-router can simultaneously generate multiple routing variants on multi-core processors (one per core) and requires fewer manual interventions.

Large schematic designs to…

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Mentor addresses heterogeneous multicore chip design

Mentor Graphics has addressed the challenge of heterogeneous multicore system-on-chip (SoC) development with a range of embedded software tools.

Heterogeneous system architectures, which combine two or more different types of microprocessors or microcontrollers, have presented particular challenges when developing embedded software to run efficiently on the multi-core…

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Cadence addresses extraction issues of finfets and double-patterning

Cadence Design Systems has enhanced the performance of its parastics extraction tool to address the challenges of chip design using double patterning process technology and finfets.

The tool is used in digital and analogue chip design to calculate resistance and capacitance parasitics of on-chip interconnect.

And the reason for…

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Synopsys upgrades auto grade NVM IP

Synopsys has introduced non-volatile memory (NVM) IP for high-voltage processes used typically for automotive ICs.

Called DesignWare AEON Trim, NVM IP is designed to be compact and is available in standard 180nm 5V CMOS and Bipolar CMOS DMOS (BCD) processes without a need for additional masks or process…

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Free IC verification event attracts big names

IC design conference, entitled Accelerating Verification – faster, smarter? is being held on Wednesday 25 June at CFMS, an independent centre for modelling and simulation located on the Bristol & Bath Science Park.

The free of charge one-day event, which is being organised by the NMI, is sponsored by design…

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DAC: Design kits speed Synopsys prototyping

Synopsys has announced intellectual property (IP) prototyping kits, virtual development kits and customised subsystems to accelerate prototyping, software development and the integration of IP into SoCs.

Under the brand ‘IP Accelerated’, the firm’s aim is to give designers a flying start by providing them with working products they can…

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