3D chip design explored by Mentor Graphics

Testing 3D ICs requires a new approach where testing IO and logic-to-logic interconnect and logic-to-memory connections are the new challenges, writes Ron Press

I remember an episode of the Simpsons where Homer drank some strong concoction and entered the third dimension. The image looked very impressive. Homer took a few steps, looked around, and then said “wow, this feels really expensive!”  

That is pretty much the situation that we have with 2.5D and 3D design; the technology promises dramatic improvements in power, performance, and integration within one package but with inherent costs and risks. One of the particular costly areas is production test.

Testing 2.5 and 3D ICs requires new types of test features and approaches. Specifically, testing , IO and logic-to-logic interconnect; and logic-to-memory connections are the new challenges.

In many mathematical applications, adding an additional dimension increases the complexity by an order of magnitude. Fabrication and test of 3D devices is quite a bit more expensive than normal packaged die because multiple die are being assembled together.

Therefore, if you waited until the package is fully assembled to thoroughly test the device, any individual failure in any of the die or interconnect would ruin the entire package. 

For example, consider the production of 10,000 3D devices that are composed of four die each. If each of the four die have a 5% probability of being defective then 2,000 of the 40,000 die used to make the 10,000 3D devices would be bad.

However, if they are not detected prior to the 3D device assembly then the 3D device has .954 probability of being defect free. Out of the 10,000 3D devices, 1854 would be defective.

With four die in each 3D device, that means that 7420 die would be discarded. In other words, 5420 good die would be thrown away. This is an unacceptable loss.

It is clear that die need to be thoroughly tested prior to packaging in a 3D device. In addition, there are opportunities for a manufacturing defect to occur at every intermediate packaging step.

So, interim tests of progressive packaging steps are useful to detect defects prior to adding additional die to the device. One particular challenge is the desire to test a TSV or interposer that is only connected on one side to a die during interim packaging of the device. 

One obvious issue in testing 2.5 and 3D devices lies in the difficulty of access; tester interfaces to devices are only available through the bottom die. 

Thus, a test interface port must be established through the bottom die to allow test of any die in the package and of the interconnects between the die.

A logical port for the basic test interface is the IEEE 1149.1 Test Access Port (TAP). This is a test control structure that is common in many devices and can be reused for special instructions and test modes used during 3D testing. 

The TAP structure provides a control system such that any one die TAP can be put in a test mode while TAPs in the other die are bypassed. The TAP is also used to support a “scan switch network” that enables scan patterns for any die to be reused and applied to that die within the 3D device.

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A diagram of a scan switch network. 

This test structure conforms to the IEEE 1149.1 standard with some additional instructions. A nice benefit is that the structure is common in any of the die on the 3D device, regardless of their location in the stack.

It also supports use of the die in a standalone package without changing the test logic.  The additional TAP instructions are used to first tell the bottom die if it is to enable the TAP of the next die in the stack or use an internal test mode such as perform memory, logic BIST, or support scan patterns. 

All test structure logic in the TAP instructions and scan switch network can be modeled with IEEE P1687, also known as IJTAG. As a result, each TAP and test logic can be easily mapped to the device level for test access and control. 

Memory die and their interface to logic die can be tested using memory BIST that is embedded in the logic die. The memory BIST design will test through interface logic to the memory die that is hosted on the logic die such as PHY and DDR logic. 

For testing logic-to-logic interconnect, one approach is to use bidirectional (bidi) boundary scan cells at each interface. The bidi cell naturally provides a wrap-around or loopback test close to the die for wafer test.

In addition, the bidi provides the ability to support a contactless leakage test for wafer test. Plus, the test structure and control language can be modeled with P1687. 

A contactless leakage test [Sunter, ITC 2001] uses the existing capabilities in the TAP and bidi boundary scan cells. It works by driving an initial state out of the bidi, disabling the bidi enable, then capturing the bidi input a specified time later. Timing from bidi tri-state to capture is controlled by the TCK frequency and the Run-Test/Idle cycles between Update-DR (tri-state bidi) and Capture-DR (measure bidi input). 

The time which the initial state on the bidi pad dissipates provides a measure of the IO leakage current and capacitance of the pad and metal connected to it. 

When testing interim packaging steps, the boundary scan tests can be performed so that they detect shorts between any two device pins. Testing open contacts or nets in the interim packaging steps is a bit harder.

Currently, we are performing research to test the viability of contactless leakage test for such an application.

Another test method being investigated for this purpose is IOTest  [Sunter, ITC 2011] with even finer resolution and the potential to detect partially open or short TSVs/interposers. These tests present a promising method to test TSVs or interposers.

As a result, costly further packaging steps can be avoided by finding manufacturing defects in TSVs or interposers or their contact to packaged die. 

While moving to 3D logic test methods can sound daunting, there are already some practices in place. I believe testing 3D ICs will have a better outcome than Homer’s foray into the third dimension, which ends up collapsing on itself.

Author Ron Press is technical marketing manager for the Mentor Graphics silicon test systems group. 

www.mentor.com

Tags: chips, EDA, Mentor Graphics, test

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