Called Virtuoso Advanced Node, the mixed signal chip design tool addresses 20nm design issues such as layout-dependent effects (LDEs), double patterning, colour-aware layout and new routing layers.
“Moving to smaller geometries always creates new obstacles, but the move to 20nm has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28nm on the same circuit,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence.
The aim has been to reduce the tasks that are needed for 20nm designs.
The tool is designed to work with Cadence’s Integrated Physical Verification System (IPVS), the tool firm’s foundry-qualified technology for signoff DRC and DPT checking. The intention is to provide design checks that reduce layout iterations.
“Engineers can build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end,” said Cadence.
The tool allows designers to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle. LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics — are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.
“By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way,” said Cadence.
Double patterning and colour-aware layout
Double patterning, a manufacturing requirement at 20nm, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “colouring” challenges to designers.
Virtuoso Advanced Node provides real-time automated colour-aware, design-rule-driven layout.
“Engineers the ability to match, lock and store colours on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix,” said Cadence.