Cadence agrees Jasper Design acquisition
Cadence has recognised the growing use of formal analysis to complement traditional verification methods.
“With verification representing over 70% of the cost of developing a system-on-chip, it has become the top system and SoC development challenge and is the critical factor for time-to-market,” said Cadence.
Jasper’s formal analysis solutions are used by customers today alongside Cadence’s metric-driven verification flow in a verification platform.
The verification platform will be integrated with Cadence’s common debug analysis, formal and semi-formal solutions, simulation, acceleration, emulation and prototyping platforms.
“Jasper’s products are recognised as the technology leaders in formal analysis, targeting complex verification challenges and increasing overall verification productivity,” said Charlie Huang, senior v-p of the system & verification group at Cadence.
Cadence intends to finance the transaction with available cash and an existing revolving credit facility. The transaction is expected to close in the second quarter of fiscal 2014, subject to customary closing conditions including regulatory approvals.