Cadence CEO tells Electronics Weekly about a culture change at the EDA firm
Lip-Bu Tan became president and CEO of Cadence Design Systems four years ago when the design tool company was in an EDA market which had not grown for almost a decade, and it was struggling to keep pace with process technology development.
Today the EDA firm is pushing tools to advanced 20nm and 14nm process nodes using finfet, fully-depleted silicon on insulator (FD-SOI) and 3D chip technologies. It has major partnerships with ARM, IBM and TSMC on process technologies and it has a growing business licensing silicon IP.
“I have spent the last four years focused on and investing in the core EDA business,” said Tan.
“The company has moved from a position of lagging behind at 65nm and 40nm process nodes to taking a lead in today’s advanced nodes,” said Tan.
According to Tan, an important change for the EDA company is its partnership with processor firm ARM.
“Today 70% of new ARM development is on our tools,” said Tan.
According to the companies, this test chip resulted in several optimisations between manufacturing process, design IP, and design tools, which will be critical for production of 16nm chips.
The 16nm process using finfet technology required new design methodologies. For example, the design flow tackled RC extraction for 3D transistors, complex resistance models for interconnect and vias, quantised cell libraries and double patterning across more layers.
The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros.
Cadence is also working with IBM and ARM to develop first processors on a fully-depleted silicon-on-insulator (FD-SOI) semiconductor process technology.
“We are now ready for people to scale with FD-SOI, finfet and 3D ICs,“ said Tan
The other big change for Cadence has been its move into the silicon intellectual property (IP) business.
This means the company not only provides the IC design tools, it can also offer the designer the main digital and analogue IP blocks which make up a system–on-chip (SoC) design.
Everyone realised that Cadence was serious about building an IP business when earlier this year it acquired Tensilica, the configurable processor firm which has audio and baseband processors in smartphones, e-readers and tablets. “Tensilica is a beautiful platform on which we can build,” said Tan.
“In four years we have moved into the IP business, we offer memory IP, verification IP (VIP) and design IP,” said Tan.
The company has VIP for AMBA, PCI Express, USB, SATA and MIPI protocols. Its silicon design IP includes controllers, serdes layer and device drivers.
Tan is not planning a quick move into being a provider of embedded software, a move other EDA firms have made.
Tan said the decision to be a provider of silicon IP came about because its customers where looking to outsource more IP. “In the area of embedded software, we are not seeing the same pressure from the customer,” said Tan.
But being a provider of embedded software is definitely on the radar, it is only a matter of timing. Last year Tan recruited Jim Ready, past founder of embedded Linux firm MontaVista, to map out a possible move into embedded software.
“We will do something, we are waiting for the right time,” said Tan.
Tan, who came from the venture capital side of the business, has also committed significant investment in technology and people, for his plan to change the culture of the company to be more “entrepreneurial, in looking for new ideas”, said Tan.
“Last year we recruited 700 people and in the first quarter of this year we have added a further 200 people,” said Tan.
Forty-six of these are what Tan called “top talent”.
“And the acquisitions we have made are not just about the assets, it is about the talent,” said Tan. “As a company we are open to new ideas from these acquisitions.”
Cadence has recently acquired the IP design team of Poland-based microcontroller specialist Evatronix.
It is also negotiating the acquisition of Bangalore-based firm called Cosmic Circuits which will give it a group of analogue and mixed signal IP designers.
Are there new areas of interest for the company, particularly in Europe?
“Low power design and mixed signal is very important in Europe, and MEMS [micro electromechanical systems) too. There is an opportunity for us here,” said Tan.
“I have changed the culture of the company to become a platform for innovation,” said Tan. “We are looking five to seven years ahead to see what the market will need.”
“The EDA market is an exciting place to be,“ said Tan.
Tags: cadence virtuoso, chip technologies, Richard Wilson, test chip