Cadence has design flow for SMIC 40nm process

Cadence Design Systems has introduced a chip design reference flow for SMIC’s 40nm manufacturing process. 

Targeting SoC designs for handheld consumer electronics products such as tablets and smartphones, the SMIC-Cadence flow is notable for its automated power management features.

“By using this interoperable, low-power, Common Power Format-based flow from RTL to GDSII, design teams can achieve faster time-to-volume for advanced low-power 40nm designs,” said Tianshen Tang, v-p of SMIC Design Service. 

The methodology is incorporated across the Cadence RTL to GDSII flow, which includes Encounter RTL Compiler, Encounter Conformal Low Power, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, Cadence QRC, Cadence CMP Predictor and Cadence Physical Verification System.

“Cadence and SMIC have teamed to enable joint customers to benefit from a comprehensive set of digital technologies such as flat power aware implementation with timing and signal integrity closure, power domain aware physical synthesis, closed loop low-power verification and physical verification,” said John Murphy, group director, Strategic Alliances at Cadence.


Tags: Cadence, China, chips, design, EDA, SMIC

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