Cadence move for Denali is part of wider silicon IP plan


At the heart of Cadence Design Systems’ move to acquire chip IP design verification specialist Denali is that software IP and not process is now the key differentiator in chip design.

Make no mistake this is a big strategic move for Cadence which is prepared to pay $315m in cash for Denali.

“Semiconductor firms are asking us to integrated hardware and software elements of design in a way that has never happened before,” John Bruggeman, chief marketing officer at Cadence told EW a week before the Denali acquisition. 

This is based on a view that increasingly system-on-chip designers see their role as enabling applications using standard silicon platforms.

As part of this “seachange” in the EDA market Cadence first announced a plan to significantly expand the amount of third party design IP it offers customers.

Then it moved to buy Denali, and Cadence CEO Lip-Bu Tan said it is Denali’s “strengths in Memory Models, Design IP, and Verification IP” which will support the company’s wider plans for design IP, which he calls EDA360.

An important part of the acquisition is Denali’s Verification IP which is optimised for supporting third-party simulators.

This Cadence sees as important for its new strategy to support SoC realisation through a combination of integrated design tools and silicon IP.

Bruggeman believes in this way it is possible to reduce the cost of qualification, acquisition and integration of IP into SoC designs which is some examples “can account for as much as 25% of the total hardware design cost”.

Denali, which is based in California, has IP for PCI Express, USB, NAND flash and DDR SDRAM subsystems.

See: Cadence offers silicon IP as part of SoC platform initiative

Tags: Cadence, design, EDA, IP

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