Cadence provides interconnect verification tool for ARM-based chips
Cadence Design Systems has introduced a software tool which can provide cycle-accurate analysis of interconnects in the design of ARM-based system-on-chip (SoC) devices.
Called Interconnect Workbench, teh tool can be used to identify design issues under critical traffic conditions, and it can be used in conjunction with Cadence Interconnect Validator and a complete suite of AMBA Verification IP for functional verification of ARM-based SoCs.
“Ensuring that on-chip interconnects perform optimally is a baseline requirement for today’s complex SoCs, system designers need the cycle-accurate analysis that Interconnect Workbench provides to make trade-offs and enhance their designs,” said Andy Nightingale, director, System IP Products, Processor Division at ARM.
Cadence and ARM will also discuss the Interconnect Workbench in a technical session titled “Measure and Optimize System Performance of a Smartphone RTL Design” at ARM TechCon on October 30, 2013.