Cadence speeds timing signoff with parallel computing

Cadence Design Systems claims to have taken a new approach to timing signoff with a new static timing analysis and closure tool for system-on-chip (SoC) development.

Cadence Tempus

Called Tempus Timing Signoff, has been designed to speed up signoff of complex chips by using a distributed parallel timing engine which can scale to utilise up to hundreds of CPUs.

Also new is the implementation of path-based analysis which Cadence says can reduce design “pessimism by up to 3%”.

There are also improvements in accuracy, said the company, because the parallel architecture can analyse designs in the “hundreds of millions of instances without compromising accuracy”.

According to Anirudh Devgan, corporate v-p in the silicon realization group at Cadence, with large SoC designs the time spent in timing closure and signoff is approaching 40% of the overall design implementation flow.

“Traditional signoff flows have failed to keep pace with the increasing demands of achieving timing closure on complex designs,” said Devgan.

Devgan said that by using multi-processing and ECO features in Tempus it is possible to achieve timing closure in days on a design that would have taken several weeks with traditional flows.

The Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.

Cadence will introduce the tool at DAC, June 3-5, 2013 in Austin, Texas.

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