Cadence tool adds power analysis to timing signoff
Cadence Design Systems continues to address the issue of signoff of complex chip designs with a tool which allows for power analysis earlier in the design cycle.
Following the introduction of its Tempus timing signoff tool earlier this year, Cadence has announced the Voltus IC Power Integrity tool which, when combined with other package, PCB and system tools, allows designers to address power management issues throughout the product development cycle.
According to KT Moore, group director, silicon signoff and verification at Cadence, this will result “in faster design signoff and closure”.
“We believe there is a need for innovation in design signoff and we can now provide combined power and timing analysis early in the design circle,” said Moore.
“Analysing power and timing simultaneously is becoming a requirement at advanced process nodes, 16nm and maybe even 20nm,” said Moore.
Like Tempus, the new power analysis tool gets its scalability from using distributed parallel processing.
“The tool’s hierarchical architecture, coupled with the parallel execution, scales to multiple CPU cores and servers, enabling the analysis of designs of up to a billion instances,” said Moore.
It uses SPICE technology and physically-aware power integrity optimisation, such as early rail analysis, de-coupling cap and power gating switches, that improves physical implementation quality and speeds up design closure