Cadence tool for on-chip power sign-off
Called Voltus-Fi, it is intended complement Cadence’s Voltus IC power integrity tool, which is a full chip, cell-level power sign-off tool, for a combination that will cover analogue and mixed-signal designs with mixed transistor-level and cell-level blocks.
Under the hood is the firm’s Spectre transistor-level SPICE sign-off simulator, and it is designed to work with Quantus QRC transistor-level parasitic extractor, and Spectre APS partitioning simulator.
“Quantus QRC solution performs electro-migration-aware extraction. It understands electro-migration rules that foundries dictate on various layout patterns. Its use is strongly recommended for the Voltus-Fi solution,” said Cadence. “Spectre APS solves the matrix for the RC power network, and the Voltus-Fi solution then runs electro-migraton and IR drop simulations based on foundry rules.”
Spectre APS can do some EM and IR drop analysis on its own, but “without Voltus-Fi, designers will not be able to look at layouts and back-annotate to the Virtuoso flow for analysis and fixing”, said Cadence.
Voltus-Fi takes current information solved by Spectre APS and uses its knowledge of the layout to evaluate compliance with migration and drop rules.
“Electro-migration [EM] and IR drop are becoming more serious problems at advanced process nodes, and foundry rules are extremely complex at 28nm and below,” said Cadence. An EM analysis solution calculates the current on each wire and compares it to foundry EM rules. The Voltus-Fi solution analyses EM and IR drop on both signal and power nets.”
Voltage drop results from Voltus power analysis can be used by the Cadence Tempus timing sign-off tool.
- A patented voltage-based iteration method, claimed to require a smaller memory footprint and to run faster than “the industry’s traditional current-based iteration method”, said Cadence.
- Visualisation on real physical layouts for analysis, debugging and optimisation, through the firm’s Virtuoso design flow.
Voltus-Fi replaces Virtuoso Power System, for better accuracy and integration with Virtuoso, said Cadence.
Electro-migration is the unwanted transport of material due to movement of ions in a conductor, caused by a transfer of momentum from electrons to these ions. One result is that high-density current in a narrow metal wire may destroy the wire. This reliability problem could occur after years of deployment in the field.
IR drop is an unwanted drop in voltage caused by current through a metal wire. An unexpected voltage drop on an instance or a device can cause a functional failure because the lowered voltage supply may not be strong enough to switch the instance, or may switch it too slowly. IR analysis calculates the IR drop and shows real voltage values on devices.
Tags: Cadence, EDA, semiconductors