The biggest challenge in complex SoC design is verification. How are designers in Europe tackling complex chip verification?
Alexander Duesener: As process nodes shrink and SoC complexity grows, IC verification becomes more and more challenging. Studies have shown that verification and debugging can consume most of the IC design cycle.
Breaking through this bottleneck, while at the same time ensuring product quality and reliability, is crucial to success in European strongholds such as wireless and automotive.
Fortunately, there are various standardised methodologies that can help. For example, more and more design teams in Europe are adopting metric-driven verification, which makes it possible to create an executable plan, track coverage metrics, and intelligently drive the verification effort until coverage goals are reached.
This can be complemented by the Universal Verification Methodology (UVM) providing an industry-standard way to develop verification environments.
While techniques such as coverage metrics, verification planning, and assertions were developed for digital IC verification, they are beginning to see adoption for mixed-signal SoC verification as well.
And finally, instead of re-inventing the wheel, most system and SoC development teams rely on so called verification IP (VIP), which provides ready-made verification environments for standard protocol interfaces like USB, PCIe, etc.
In which areas of chip design is IP integration and re-use having the biggest impact?
Alexander Duesener: IP integration and re-use is having a profound impact on complex SoC design. Many designs are comprised primarily of reused or externally sourced IP blocks. This allows designers to focus differentiating their products.
Over time, IP blocks are getting bigger and more complex. Yesterday’s chip is today’s IP block.
One consequence is the emergence of more and more mixed-signal IP blocks – not purely analogue, not purely digital, but both interacting together to serve functions such as video, audio, and image processing.
Meanwhile, IP “subsystems” comprised of several integrated IP blocks are starting to emerge.
One important aspect of IP is configurability. The IP must be fitted to the SoC, not the other way around. IP quality also remains a concern, and a reputable provider with strong domain expertise is a must.
How has the way in which designers use EDA tools changed in recent years?
Alexander Duesener: For many years the EDA industry was largely focused on point tools.
While individual tool capabilities continue to be important, in recent years the focus has begun to shift to end-to-end, integrated design techniques for challenges such as low power and mixed-signal implementation and verification as well as IC/package co-design.
Such techniques are critical because chip and system design has become too complex for patchwork design flows that require file format translations from one tool to another. Going beyond tool translation issues, common engines for physical optimisation, verification and prototyping, and signoff-quality analysis are becoming increasingly important.
This is not to say that design teams don’t use third-party or internally developed tools, many do. Industry standards such as the OpenAccess database make such usage easier.
But the emphasis is shifting from “tools” to “solutions” that can solve complex problems. Tool capability is still an issue, but it’s important to look at a bigger picture when evaluating EDA tools.
Do European designers have easy access to leading foundry services?
Alexander Duesener: Yes, they do. The leading foundries have distinct foundry access and service strategies to serve the European customers. They directly take care of their key customers and have partnerships in place for smaller, emerging and medium size customers.
TSMC for instance works with e-Silicon, Global Unichip as well as IMEC act as aggregators who offer foundry access, as well as the relevant backend services, like packaging, assembly and test.
Gobalfoundries and IBM have selected Delta, a Danish Design and testhouse, as their strategic supply chain partner who provide virtual Asic offerings.
On top of that we have a number of specialty foundries in Europe, like Altis, Austriamicrosystems, LFoundry, TowerJazz, X-FAB, etc. who offer their technologies and services directly to European customers.
So, overall, access to foundry technology and capacity, both for leading edge technology nodes as well as for legacy and specialty technology nodes, is well covered in Europe.
Is full system level design changing the way large silicon design projects are managed?
Alexander Duesener: Absolutely it is. When developing a large SoC, designers not only have to define the SoC architecture, but also need to consider the software it will run.
Semiconductor companies are expected to provide a growing amount of software together with the SoCs to their customers.
Software design teams within semiconductor companies are outgrowing the pure chip design teams.
Within system companies the availability of hardware has traditionally been a gating factor for software development. With latest virtual prototyping and hardware assisted prototyping technologies, software design and verification can be accelerated significantly.
Software and hardware can both be debugged to a large extend before silicon is available.
In my view, a hardware-software co-design and verification strategy is central to meeting today’s time to market realities and requires careful project ma nagement.
What is biggest opportunity and focus in the European design community?
Alexander Duesener: With the changing industry landscape in Europe there is a clear trend towards application specificity. We are applying technologies to specific application domains. Automotive and industrial is big in Europe.
The “Internet of Things” provides a vast new area of interesting opportunities, and again requires strategies for ultra low power, mixed signal design, combined with system-level and software aspects of how to connect all the devices to the network.
European developers will discuss critical design and verification issues at CDNLive EMEA in Munich May 6-8.