Chip emulation enters multi-project world, says Mentor
Complex chip design simulation and emulation is moving out of the engineering lab to become a global resource which can support multiple projects.
Emulator supplier, Mentor Graphics believes this will dramatically change chip design by making emulation more accessible and cost-effective.
“Increasing hardware and software complexity in system on chip design requires increased emulation engine power, and emulation had to adapt to deal with these complexity challenges,” said Jean-Marie Saint-Paul, European director at Mentor Graphics.
To date the focus has been to improve the efficiency of the emulation process. “Transaction-based emulation has changed the game for us,” said Saint-Paul.
The next step was to link hardware and software simulation, but also to make it possible to reuse simulation data, which is inherently costly and time consuming to create.
“Cost of emulation has dropped in ten years, cost per gate has dropped massively, but we knew we could go further,” said Saint-Paul.
To be more affordable as a design tool, Mentor believes emulation must change from “project-bound engineering lab instrument to datacentre-hosted global resource”.
The next step was to create virtual emulation environments running on enterprise servers which can be accessed by more than one design project.
“The aim now is to make more efficient use of processing power,” said Saint-Paul.
The start of this process is removing the need for the in-circuit emulation (ICE) tangle of cables, speed adaptors and physical devices, replacing them with virtual devices.
These virtual devices, which Mentor calls VirtuaLab peripherals, are hosted as central resource within a company or even shared between companies in a datacentre. The software-defined peripherals can be configured for multiple projects.
Another part of the process is more closely coupling chip design verification, simulation and emulation and to move it all to become a datacentre resource.
Mentor calls this the Enterprise Verification Platform (EVP) which combines Questa verification tools, Visualizer debug environment and the Veloce OS3 VirtuaLAB peripherals for the first time.
With Veloce OS3 and Questa 10.3, assertions, coverage and runtime data from emulation, formal, simulation, mixed-signal and low power design are stored on the centralised database.
The virtual platform runs under the Veloce OS3 which manages the emulation resources by creating priority queues to make most efficient use of the resource.
The aim is to make complex chip emulation more affordable to remove the need for costly, dedicated hardware emulators for each project.
Smaller chip design firms may not need to investment in costly emulation systems. They could get their designs emulated by third party emulation service providers. Much in the same way firms use foundries to fab chips.
Saint-Paul believes there are security and IP licensing issues to be address but he sees the potential for this.
Another interesting possibility is using emulation to market chips before they are produced.
“”There could be a benefit of emulation for marketing. A design could be shared with customers earlier in the design cycle,” said Saint-Paul.
Another benefit of Veloce OS3 is it creates in the emulator PSL/SystemVerilog assertions, functional coverage, and UPF for low power.
This can be used to provide pre-silicon performance analysis of critical on-chip subsystems running application software.