Under the brand ‘IP Accelerated’, the firm’s aim is to give designers a flying start by providing them with working products they can modify.
The prototyping kits consist of a pre-verified reference design IP implemented on emulation hardware.
In the box, there is the firm’s HAPS-DX prototyping board with pre-configured IP and SoC integration logic, a PHY daughter board, simulation test bench, an ARC-based software development platform running Linux, reference drivers, and application examples.
“Designers can modify the standard IP configuration for the target application through an iteration flow consisting of coreConsultant IP configuration tool, ProtoCompiler DX synthesis and debug tool, and compilation scripts,” said the firm.
The virtual development kits are a configurable model of the DesignWare IP and a multi-core ARM Cortex-A57 Versatile Express-based reference design. They run Linaro Linux and include reference drivers for the DesignWare IP.
“For software developers, both the virtual development kits and IP prototyping kit can be used as proven targets for early software bring-up, debug and test in parallel with SoC development. Out-of-the-box support for a Linux software stack ensures that software developers are up and running instantly and can focus on bring-up and validation of the IP-specific software: drivers, bootcode, firmware, for example,” said Synopsys.
The kits can be extended to represent the full SoC, enabling development of the entire board support package (BSP).
Why doesn’t Synopsys just provide drivers for its IP? “Software developers need to optimise the drivers for the specific configuration of the IP and the operating systems. Drivers can have a dramatic impact on performance of the protocol. A non-optimized driver can decrease throughput by 20% to 40%,” it said.
For those wanting the IP from the DesignWare portfolio, but not wanting to integrate it, the firm will customise it and integrate it into the customer SoC. This includes SoC-level integration (clocks, reset, interrupts, DMA, memory maps, power management blocks), sub-system integration (controller and PHY IP integration into the SoC), multi-protocol integration and SoC verification (integration of verification IP into the SoC verification flow).
The first kits are scheduled to be available in July, and are on show at the Design Automation Conference (DAC).
There are a couple of IP Accelerated videos.