DAC: Flexras compiler partitions multiple FPGAs

Flexras Technologies, a French design tool firm specialising in partitioning for FPGA-based prototyping, has announced a complier which it claims can boost multi-FPGA design performance.

Wasga Compiler is a timing-driven, multi-FPGA partitioning software for Asic and SoC prototyping.

The compiler partitions large designs onto multiple FPGAs, taking into account clock frequency constraints required for running software applications in near real time. 

It will handle multi-billion Asic gates equivalents designs, and maps them to an  Altera or Xilinx board.

“Multi-FPGA platforms are heavily used for Asic and SoC rapid prototyping. Existing tools notoriously fail the complex partitioning challenge,” said Hayder Mrabet, CEO at Paris-Saint Denis based Flexras

“Verification engineers still rely on a cumbersome manual partitioning methodology,” said Mrabet.

The key for this compiler is in FPGA-based SoC prototyping is its automatic partitioning.

“Engineers benefit from high clock frequencies and fast execution time,” said Mrabet.

Flexras will demonstrate Wasga Compiler at DAC 2012, June 4-6, 2012, Moscone Center, San Francisco.

The Wasga Compiler is available now. For pricing please email sales@flexras.com

Tags: Asics, dac, design, EDA, FPGAs, tools

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