Design-then-fix no longer works, says Mentor

Guest columnists Sudhakar Jilla and Jean-Marie Brunet from Mentor Graphics believe that an EDA platform that can optimise for both manufacturing variations and traditional timing can address the design sign-off bottleneck.

As we move into sub-40nm designs, manufacturing closure is becoming a major bottleneck. The traditional tools and methods used to complete a physical IC design and make it ready for manufacturing sign-off are under stress.

New approaches are needed to eliminate late-stage surprises and file-based iterations between tools, to fix violations in the context of timing, SI and power, and to use engineering resources more efficiently.

Sources of sign-off problems
Layout features at sub-40nm are more difficult to transfer to wafer mainly due to limitations in the exposure systems of steppers, which have been stuck with 193nm wavelength light since the 130nm node.

Certain shapes and combinations of shapes in close proximity are particularly problematic. To maintain yield semiconductor manufacturers are being forced to tighten up their design rules to ensure that physical features susceptible to these effects are not introduced into the design (Figure 1).


They are also making model based design for manufacture (DFM) analysis mandatory, so designers are more responsible for ensuring a design is manufacturable. As a result, the amount of design rule checking (DRC) and DFM procedures that must be passed to achieve manufacturing closure, or “sign-off,” is increasing.

The traditional flow, which consists of completing the physical design followed by physical verification checks and DFM improvements, is based on a key assumption: that the place-and-route tool can get close enough to make physical sign-off predictable.

In the past, this was a reasonable assumption and the methodology worked. But at sub-40nm it begins to break down. Previous generations of router were just not designed to handle so many new and complex rules.

In addition, late changes made after layout, such as DFM enhancements, can have “ripple effects” – ie, they can lead to new manufacturing violations, or negatively affect the performance targets of the design.

For example, adding metal fill to improve planarity or moving wire edges to remove a pinching condition can degrade timing and signal integrity as parasitic interactions change.

A new platform is needed that can concurrently optimise for both manufacturing variations and the traditional timing, SI and power metrics.

Another problem is a growing disconnect between design and sign-off models. The “golden” foundry sign-off models expressed in SVRF language are the most accurate.

These models are constantly being updated as the process matures. Design models are typically simpler abstractions of sign-off models to permit better runtime/accuracy trade-offs. They also tend to get out of sync with the sign-off models, which could lead to late stage surprises at sign-off.

In addition, at 28nm and below, there are some rules described in SVRF that simply cannot be expressed in the simpler formats used to describe design models. 

As a result, implementation tools may report the layout as DRC/DFM-clean but the sign-off physical verification tool will flag violations.

These challenges are exacerbated by the fact that there is no automated way to repair DRC/DFM violations and the traditional flow requires the transfer of huge ASCII files between the implementation and sign-off environments for each iteration.

Sign-off in place-and-route
At 28nm and below there is a need for a platform that integrates physical design and manufacturing sign-off for a true correct-by-construction approach. An effective manufacturing closure solution must:

– Minimise the design-to-sign-off model gap by reading the actual golden sign-off models as needed. 
–  Be able to invoke any sign-off DRC/DFM engines during design to guarantee no surprises at sign-off
– Automatically fix any sign-off violations that are identified concurrently with the traditional design metrics like multi-mode multi-corner timing, SI, and power. 
–  Eliminate ASCII data transfers through data model integration.

Such a system integrates physical design, verification and DFM operations into a single platform by allowing the sign-off analysis engines to be invoked directly from the place-and-route environment, so that manufacturing issues are identified and automatically fixed concurrently with the design process.

Not only are manufacturing issues addressed earlier in the design process but trade-offs between timing, SI, power and manufacturability are considered simultaneously to achieve a properly optimised design.

The demands of manufacturing closure at advanced process nodes make a traditional design-then-fix flow increasingly ineffective. An efficient answer is for DRC/DFM analysis to use the foundry-approved SVRF sign-off rules and engines, integrated directly with the place-and-route system.

It should also provide automated repair and on-the-fly re-verification to ensure that all fixes are sign-off-clean without manual fixing.

Finally it must be able to optimise for DRC/DFM metrics in the context of traditional timing, SI, and power targets. With a sign-off-guaranteed approach, design closure times can be reduced from weeks to days.

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