French firm designs three billion transistor processor array
Kalray has completed the design of a three billion transistor processor array and it used a Mentor Graphics functional verification, physical design and verification, and design-for-test flow.
The France-based fabless semiconductor company’s 256-core SoC is implemented using 28nm manufacturing process technology.
“Our design methodology is based on a multi-level hierarchical approach in order to optimize performance, to take advantage of a modular and repetitive design and to overcome implementation complexity,” said Joël Monnier, CEO at Kalray.
Kalray’s Multi-Purpose Processor Array (MPPA)-256 processor is fabbed by TSMC. Product qualification is scheduled for completion in Nov 2012.
The company is backed by French investment funds, local funds, private investors, and OSEO, a French public-sector institution who finance innovative projects brought by SME’s.
The first MPPA-256 processor integrates 256 processors onto a single silicon chip. The multicore processor is organised as 16 clusters of 16 processors and multiple MPPA chips can be interconnected at the PCB level through Interlaken interfaces to increase the processor array size and performance capability.
Kalray employed an OVM-based functional verification methodology using the Mentor Questa product, which provides AXI protocol support in the Questa
Verification IP Library.
For physical design (layout), they chose the Olympus-SoC place-and-route system for its ability to handle large capacity hierarchical designs with multithreaded
routing and timing analysis, multi-corner multi-mode based multi-voltage flow, and built-in Calibre signoff inside the Olympus-SoC system.
“The fact that Mentor’s platforms work together seamlessly is a definite productivity enhancer, but just as critical, each tool needs to have the features, speed, accuracy and capacity to handle designs at this scale,” said Monnier.
The Kalray processor cores implement a proprietary VLIW architecture with advanced low-power design techniques, and integrate a high-performance IEEE 754 floating-point unit.
Kalray ran DRC in multi-threaded mode with up to 160 CPUs to reduce turnaround time.