French processor IP designed for multi-cores
Cortus, the French processor IP firm, has developed a 32-bit core which can be used in dual or quad-core configurations.
The APS5 processor IP is designed as a high performance core with integer unit and an instruction cache.
“Despite its modest CPU core area, the APS5 delivers 2.29DMIPS/MHz,” said Michael Chapman, CEO and president of Montpellier-based Cortus.
In common with the firm’s other Cortus processors, the APS5 has a 5 to 7 stage integer pipeline and out-of-order completion ensuring that most integer instructions (load and stores included) are executed in a single cycle.
“The architecture enables a high maximum clock frequency, for example it is capable of greater than 400MHz in a 90nm technology,” said Chapman.
The processor is supplied with an instruction cache and a data cache is optional.
It can be used in symmetric multi-processing (SMP) configurations such as dual- or quad-core. For example, while a single APS5 core offers 1.93 CoreMarks/MHz a dual-core configuration benchmarks at 3.51 CoreMarks/MHz.
For SMP configurations a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous APS5/APS3R configurations.
The core’s silicon footprint is 0.088 mm2 in 90nm (UMC) and the toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use.
Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OS and µCLinux.