Glasgow simulates 10nm finfet ICs

The FP7 funded European consortium TRAMS (Tera-scale Reliable Adaptive Memory Systems) has completed an important milestone by analysing the statistical variability in a 10 nm channel length finfet on SOI substrate using advanced statistical TCAD simulation.


The TRAMS consortium includes: Intel, Imec, GlasgowUniversity and the Universitat Politècnica de Catalunya (UPC). Device design and simulation are being done by a GlasgowUniversity team led by Professor Asen Asenov who developed the simulation software which uses grid computing linking thousands of computers to simulate the behaviour of billions of individual transistors in an IC.


The TRAMS finfets are designed to fulfil the ITRS requirements for the 11 nm CMOS technology generation. The simulations have been carried out using unique simulation technology available to the project that takes into account the major known sources of statistical variability and reliability, including random discrete dopants, the gate and the fin line edge roughness, the metal gate variability and bias temperature instability effects (e.g., NBTI/PBTI).


The results of the physical simulations have been captured in accurate statistical compact models by the TRAMS partners.  These models are being used to evaluate the impact of statistical FinFET variability on 11nm embedded memory design and to develop circuit and system countermeasures that will make future embedded memories resilient to statistical variability and reliability.


TRAMs was initiated to investigate the impact of the statistical NanoCMOS variability on tera-scale embedded SRAM memories based on sub 16 nm technology generation utilising conventional and novel CMOS devices.


The statistical variability introduced by the discreteness of charge and matter has become a major obstacle to scaling and integration.


The impact of this statistical variability on embedded memories is particularly dramatic, by slowing supply voltage scaling, especially for SRAM, and threatening the continuation of area scaling that helps drive integration targets for SOC.


Concerns about SRAM area and power supply scaling are major drivers behind the revolutionary introduction of finfet devices. TRAMs is striving to understand the implication of finfet technology on the continuation of CMOS scaling as projected by Moore’s law.




Tags: Asenov, finfets

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