Apache, the power analysis EDA specialist which was recently taken over by Ansys, is now looking outside IC design to chip packaging optimization.
One of its target applications is 2.5D and 3D packaging which aims to reduce power consumption by 4-10x by eliminating much of the power penalty of connections.
Other new areas enabled by the marriage of a chip company with the more generalized engineering simulation expertise of Ansys, is looking at increasing board performance and minimizing EMC in automotive applications.
Apache’s expertise up to now has been in bridging the performance and power budgets of ICs.
“The requirement for getting into the socket of a mobile phone is you have to be under 5W,” Andrew Yang, President of Apache, told the Summit, “while Qualcomm says cores need to work at 2.5GHz. So you have to decide: Are you going to be a leader in performance, or in power or in price All semiconductor companies have to ask this question.”
“If you do nothing, the power gap increases by 2x every two years,” said Yang, “there are three challenges: estimating the power budget at an early stage in the architectural process before any physical data is available; making sure the power is delivered to the right place at the right time; and minimizing power-induced noise.”
Apache has a 70% market share in its niche of IC power analysis. Asked how Apache managed such a dominant position when up against big players like Synopsys, Yang replied: “We’ve defined our niche and deliver a best in class product, and we run fast – we’re two to three years ahead of the opposition.”