Hard IP support for Lattice PLDs
Lattice has released serial interface and programming reference designs for the hard functions in its MachXO2 programmable logic devices (PLDs).
Named the embedded functional block (EFB) the hard IP includes I2C, SPI and flash.
The reference designs are ready-to-use RTL code, each with standard data and command interfaces.
I2C-slave (design number RD1124)
UFM access (RD1126)
Embedded programming (RD1129)
The RTL code is commented and parameterised to allow it to be customised.
For existing development boards, there are also five new demonstration designs focused on the same hardware:
I2C master with I2C slave (UG55)
SPI master with SPI slave (UG56)
Master I2C & SPI using C and the LatticeMico8 microcontroller (UG54)
Programming via the open-source Wishbone Bbus (UG57)
Embedded programming via I2C (UG58)
“These designs, each with commented, pre-verified RTL and C, are re-usable to help engineers get a head start on their own implementations,” said the firm.
Lastly, some MachXO2 guides have been updated:
TN1204 – Programming and configuration usage
TN1205 – Using user flash memory and hardened control functions
TN1246 – Using user flash memory and hardened control functions devices reference