Semiconductor design is starting to see the adoption of 3D IC packages. These packages involve stacking multiple bare die vertically using connections that go directly though the silicon. Through-silicon vias (TSV) result in shorter and thinner connections that can be distributed across the die.
This reduces package size and power consumption while increasing performance due to the improved physical characteristics of the very small TSV connections compared to the much larger bond wires used in traditional packaging. But TSVs complicate the test process and 3D ICs require new approaches to solve this problem.
A challenge is how to test the TSV connections between the stacked memory and logic die. There is generally no external access to TSVs, making the use of automatic test equipment difficult at best.
Functional test approaches (for example, where an embedded processor is used to apply functional patterns to the memory bus) are possible but are slow, lack test coverage, and offer little to no diagnostics. Therefore, ensuring that 3D ICs can be economically produced calls for new test approaches.
Tackling this can not be put off. Applications involving the stacking of one or more memory die on top of a logic die, for example using the JEDEC Wide IO standard bus interface, are ramping quickly.
One possible approach to the test and diagnostics challenges of memory on logic TSV connections builds upon built-in self-test (BIST) techniques that are used to test embedded memories within system-on-chip (SoC) devices.
In this approach to 3D test, a BIST engine is integrated into the logic die and communicates to the TSV-based memory bus that connects the logic die to the memory.
For this approach to work, two different techniques to existing embedded memory BIST approaches are necessary.
One is an architecture that allows the BIST engine to communicate to a memory bus rather than directly to individual memories. This is necessary partly because multiple memories may be stacked within the 3D IC, but mostly to allow the BIST engine to test the memory bus itself, and hence the TSV connections, rather than just the memories.
Test algorithms for covering bus-related failures are used to ensure maximum coverage and minimal test time. Because of this directed testing of the memory bus, the 3D BIST engine can also report the location of failures within the bus, which enable effective diagnosis of TSV defects.
The second difference is that it is fully run-time programmable. Using only the standard IEEE 1149.1 JTAG test interface, the BIST engine can be programmed in silicon to adapt to different memory counts, types and sizes stacked on top of the logic die.
Because the BIST engine is embedded into the logic die and can’t be physically modified without a design re-spin, this adaptability becomes essential. With full programmability, no re-design is needed over time even as the logic die is be stacked with different memories and memory configurations for different applications.
An automated flow is available for programming the BIST engine (for wafer or final package testing) to apply different memory test algorithms, to use different memory read/write protocols, and to test different memory bus widths and memory address ranges. The patterns needed to program the engine through the JTAG interface pins are generated in common formats, such as WGL or STIL, to be loaded and applied by standard automatic test equipment.
Because of its embedded nature implementation of this approach relies on ensuring minimal impact on design flows and schedules and no impact on design performance.
This can be accomplished by integrating the BIST engine into the logic die and fully verifies its operation. The flow operates at the RTL level and is fully compatible with all standard silicon design flows and methodologies.
Impact to design performance is avoided as the BIST engine intercepts the memory bus with multiplexing logic placed at a point in the functional path with sufficient slack.
Engineers considering designing in 3D will want to feel confident that these can be tested without excessive delay or risk.
This embedded approach for testing TSVs between memory and logic die can provide optimisation between test time and test quality.
A 3D test white paper is available
Author is Stephen Pateras, product marketing director for Mentor Graphics Silicon Test products.