Imec and Cadence show 3D chip test tool
The tool, which is based on Cadence Encounter test software, was verified on an industrial test chip containing a logic die and a JEDEC-compliant Wide-I/O Mobile DRAM.
Memory-on-logic 3D stacks offer the possibility of heterogeneous integration with dense low-power inter-die interconnects.
Recently, JEDEC has released a standard (JESD-229) for stackable Wide-I/O mobile dynamic random access memories (DRAMs) specifying the logic-memory interface.
Unlike many previous DRAMs, the standard contains boundary scan features to facilitate interconnect testing.
The design-for-test (DFT) architecture is an extension of their previously announced logic-on-logic 3D DFT architecture and it supports post-bond testing of the interconnects between the logic die and the DRAM stacked on top of it.
It includes the generation of DRAM test control signals in the logic die and the inclusion of the DRAM boundary scan registers in the serial and parallel test access mechanisms (TAMs) of the 3D test architecture.
The design of the test chip is an interposer-based 3D stacked IC which includes a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank.
The validation results show that the silicon area of the additional DFT wrapper is negligible compared to the total logic die size (<0.03%). Moreover, the test pattern generation was very efficient (tens of patterns, generated in only a few seconds) and effective (100% coverage of the targeted faults).
All 3D-DFT logic in the logic die was automatically inserted with Cadence Encounter RTL Compiler while the Interconnect test patterns were generated with Encounter Test ATPG.
“This 3D memory-on-logic DFT solution is another big step forward toward market introduction of 3D-stacked IC for next-generation high–performance, low-power mobile applications,” said Bassilios Petrakis, product marketing director for the Encounter test product family at Cadence.
Tags: 3D, Cadence, chips, dram, IMEC