Imec works with Delft University on 3D IC design flow tool
Called 3D-COSTAR, the tool uses input parameters that cover the entire 2.5D-/3D-SIC production flow from design and manufacturing to packaging and logistics.
“It is aware of the stack build-up (2.5D versus 3D, multiple towers; face-to-face or face-to-back) and stacking process (die-to-die, die-to-wafer, or wafer-to-wafer). The tool produces three key analysis parameters: 1) product quality, expressed as defect level (test escape rate) in DPPM (defective parts per million); 2) overall stack cost; and 3) breakdown per cost type,” said Imec.
Semiconductor manufacturing is notoriously defect-prone each IC needs to undergo electrical tests to weed out defective parts. For through silicon via (TSV)-based 2.5D- and 3D ICs that typically contain complex die designs in advanced technology nodes, testing is even more critical.
“There is not a ‘one-size-fits-all’ test flow that covers all stacked-die products. The test flow needs to be optimized based on yield and cost parameters of an individual product and that is a complex optimization problem,” said Dr. Said Hamdioui, Associate Professor at TU Delft.
“And different test flows, executed after manufacturing, may require different design-for-test features, which need to be incorporated in the various dies during their early design stages.”
According to Erik Jan Marinissen, principal scientist at Imec: “We have used 3D-COSTAR to determine when pre-bond testing of the interposer in 2.5D-SICs pays off and what its maximum-allowed test cost can be. In some cases, the overall stack cost reduction amounts to 40%, showcasing that upstream testing can help avoid downstream costs. The tool also demonstrated under which circumstances mid-bond testing (on partially-completed stacks) can be avoided without compromising a high stack yield.”