It has introduced a software tool which automatically generates HDL code from MATLAB for implementing FPGA and Asic designs from the MATLAB language.
HDL Coder generates synthesisable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming.
“Engineers everywhere use MATLAB and Simulink to design systems and algorithms and now with HDL Coder and HDL Verifier, they no longer have to manually write HDL code or test benches to develop FPGA and Asic designs,” said Tom Erkkinen, embedded applications and certification manager, MathWorks.
“HDL Coder offers integration with Xilinx ISE design suite, creating a pushbutton workflow,” said Vin Ratford, senior v-p worldwide marketing and business development, Xilinx.
The company also announced HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and Asic designs.
HDL Verifier links system models to FPGA designs and enables engineers to perform FPGA hardware-in-the-loop verification with Altera and Xilinx FPGA boards.
HDL Verifier provides co-simulation interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, engineers can rapidly verify that their HDL implementation matches their MATLAB algorithms and Simulink system specifications.
“As adoption of FPGAs continues to grow across industries, designers need a way to bridge the verification gap from system models to FPGA design,” said Vince Hu, vice president of product and corporate marketing at Altera.