Mentor looks at dual approach to chip test

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer Guettaf

With the larger, more complex ICs at advanced nodes, testing your design is more crucial than ever and it makes sense to find techniques within the existing IC test toolbox.

To address the ever increasing pressure to reduce the cost of manufacturing test, efficiently use test equipment, and increase yield, an interesting approach is the combination of the two most common test methodologies currently in use.

A hybrid solution of logic built-in self-test (LBIST) and automatic test pattern generation (ATPG) compression optimises defect coverage vs. test time, reduces test pattern volume and test pattern generation time, and provides key optimisations between parallel and serial test applications.

LBIST technology inserts embedded logic into the design, for a fully integrated and automated test solution that can be used at any test step or level of integration with a simple interface. LBIST reduces test time because shift is not limited by external data;  patterns are generated on-chip and results are compressed into a simple signature.

ATPG offers high pattern efficiency due to use of deterministic patterns, low-power support, high stuck-at coverage, and support for various fault models. Using embedded test compression speeds up test, allows more patterns to target other fault models, and reduces the test interface to just a few pins.

Are LBIST and ATPG better together?

When designing for test engineers feel compelled to exclusively adopt one methodology over the other. However, the two methods really are complementary to each other and can result in the shortest test-time and very high test coverage.

For example, shift speed of at-speed deterministic ATPG is limited by the shift path length and the speed of the pad I/O used. At-speed LBIST can significantly increase the speed of the shift clock. ATPG also makes up for the low-power limitation of LBIST by enabling low-power shift, which will lower the switching activity during test by controlling the data shifted into the chains.

In terms of chip size, a hybrid LBIST-ATPG test structure has minimal area impact because the most common logic of these two test methodologies merges. The only logic that is not merged at this time is the PRPG/MISR used for LBIST and the EDT logic used for deterministic ATPG. Figure 1 is an illustration of hybrid test methodology structure.

LBIST–ATPG hybrid test structure

The hybrid test methodology is based on the concept of core isolation, which allows having two overlapping modes–external mode and internal mode.

In external mode, only the block interface/peripheral registers are connected to dedicated chains. The remaining registers, which are the core registers of the block, are not part of these external chains.

The internal mode includes all scannable registers of the blocks inside multiple chains, including the peripheral registers. To fully isolate the block from external logic, the input interface registers are kept in shift-only mode so they do not capture unknown values from the upper level.

Each core employing this hybrid test methodology flow has a 1500 IEEE interface also referred to as WTAP (wrapper test access port). This interface connects to the top-level TAP once the core is integrated in a chip. You choose the core mode by loading the WTAP with the appropriate operation code.

Multiple core BISTs may be started in parallel. If all cores have dedicated ATPG scan I/Os on the chip level, it is possible to run all of them in parallel too.

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Figure 1 is an illustration of a top-level integration in which all cores A, B, and C have dedicated scan I/Os as described above.

Some applicable test pattern configurations are outlined as follows: 

Example 1: Full parallel test, shortest tester time
• Test all cores A, B, and C in parallel using LBIST test through the TAP.
• Test all cores A, B, and C in parallel using ATPG test through TAP and scan I/Os.

Example 2: Mixed parallel and serial
• Test cores A and B in parallel using LBIST test and then test core C.
• Test all core A, B, and C serially using ATPG. 

Example 3: Full serial, longest tester time
• Test all core A, B, and C serially using LBIST.
• Test all core A, B, and C serially using ATPG.

All of the examples above are possible without regenerating a new hardware or rerunning ATPG from the top level. This time-saving advantage occurs because cores A, B, and C were created through a flow that generates both LBIST patterns and ATPG patterns at core-level boundaries.

When the cores are integrated in the top level, a tool reads the patterns previously generated at the core level and retargets them from the top level without requiring any new fault simulation or DRC check. This process is referred to as pattern reuse.
 
Amer Guettaf is a senior field application engineer at Mentor Graphics

www.mentor.com

 

Tags: chips, design, EDA, Mentor Graphics

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