The graph-based specification format is based on the standard Backus-Naur Form (BNF), pioneered by IBM, and has been used by many companies to automate compiler testing. Its natural atomic architecture closely mimics the structure of a typical design specification, making requirements mapping easy and straightforward.
The graph-based specification format being donated by Mentor Graphics has been augmented to support VLSI design verification across all standard environments and languages including Verilog, VHDL, SystemVerilog, e, SystemC, C/C++, assembly code.
“We have seen customers realize a ten-fold gain in productivity through the adoption of graph-based test technology,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics.
“Based on customer feedback, we’re moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users, and opens the door to technology innovation.”
According to Mentor, graph-based test specification can reduce the time spent writing and debugging tests. It supports multiple design languages and multiple verification environments enabling re-use across both design context and verification engines.
“The same graph-based test specification can be used in a SystemVerilog UVM testbench environment for block-level simulation, as well as in an embedded C test program for system-level emulation,” said Mentor.
Also the abstract nature of a graph-based test specification lets tool implementations execute the test specification in different ways according to verification requirements.
For example, a tool with a graph-based test specification can be instructed to execute the test specification in a systematic way to quickly achieve functional coverage during the early stages of a verification project. At a later time, the tool can be instructed to execute the test specification in a completely random manner to produce soak tests on a simulation farm for regression testing.