Mentor sees need for manufacture-compliant chip IP
As IC dimensions fall below 65nm, manufacturing variability makes it more difficult to predict yield for any particular design. Design for manufacture-compliant IP is a growing necessity, writes David Abercrombie
Design for manufacturing (DFM) techniques were developed precisely to help design houses create IC designs that yield well in the face of manufacturing process variability.
As the complexity of verifying designs has increased, so has the use of third party components.
Today’s chip designers often include multiple pieces of external intellectual property (IP) to address specialised functions (such as SRAM) that can be more efficiently produced by a company that develops and perfects one design, then migrates it to multiple foundries and process nodes.
The growth in IP is also fueled by the move to standards (such as DDR, USB, MIPI) that provide both the IP developer and the IP user with the confidence that the IP will be usable in a larger design.
But designing a large SoC with many IPs designed by multiple companies, each using a variety of design techniques and tools, makes DFM more difficult.
Each piece of IP is unlikely to have gone through the same DFM analysis and optimisation.
IP customers are starting to insist that IP vendors implement more stringent DFM assurance processes.
Also, as DFM optimisation becomes a requirement at smaller nodes, IP vendors are rapidly moving to collaborate with the foundries and EDA companies to implement and enforce IP DFM compliance and optimisation.
Several process flows and methodologies have been developed and are commonly used today. To enable automated DFM optimisation, the foundries now provide the necessary DFM kits (specialised rules decks), and suggest appropriate flows and methodologies.
Examples of DFM kits that are currently available include critical feature and critical area analysis and optimisation, lithography “hotspot” identification and optimisation through the use of litho-friendly design (LFD) tools, and planarity and fill analysis and optimisation through chemical-mechanical planarisation (CMP) simulation and analysis, and “smart” automated fill techniques.
Critical area analysis (CAA) is a well-established design process, intended to identify areas of designs that are susceptible to random defects during manufacture. By applying CAA to an IP design, IP vendors can provide assurance that the IP design has been built to avoid constructions that are particularly sensitive to the levels of random defects expected for a particular foundry process.
Foundries also provide recommended rules in the design rule manual to help designers add margin for various process effects (such as etch, stress and alignment). However, these checks can create hundreds or thousands of undifferentiated violations.
Critical feature analysis (CFA) kits driving EDA tools help designers find, prioritise, and categorise high-impact recommended rule violations in a design, providing a significant benefit over traditional DRC alone. Designers can use automated DFM tools to provide a prioritised list of high-impact recommended rule violations.
Lithography process variation is another significant DFM issue that is not adequately addressed by standard design tools or post-tapeout processing. Layout design does not usually quantify process window variations, while optical process correction (OPC) only corrects the design for the nominal lithographic process. To avoid potential lithographic issues very late in the design cycles, when fixes are extremely difficult, lithography simulation is used during the design and verification process.
Lithography simulation tools use both resolution enhancement technology (RET) and OPC information to predict silicon printed results, and also capture the foundry process window (e.g., dose and focus). Lithography simulation allows IP vendors to uncover and remove potential litho hotspots that could show up in the layout of the integrated design.
One other area of IC design addressed by DFM is that of planarity—the flatness of the IC after CMP. Designers have long used metal “fill” to achieve a more even distribution of metal across the die by adding non-functional metal shapes to “white space” regions in a design.
One purpose of metal fill is to reduce the variation in thickness that occurs during CMP. By achieving a more uniform thickness, designers can prevent interconnect shorts and opens resulting from metal pooling and dishing.
Designers need tools that can provide an optimum amount of fill without introducing excess parasitic effects. When used on IP, the tools must also be able to account for context around the physical IP when it is inserted into a full chip design.
IP vendors and foundries need to establish specifications and requirements (both in tools and processes) to define DFM quality levels, and then develop a means of communicating the results to the customers so they know:
1) the IP has been certified, and 2) precisely what that certification means. As an initial step, some IP vendors have integrated IP DFM validation with their on-going IP quality assurance process.
David Abercrombie is the programme manager for advanced physical verification methodology at Mentor Graphics