While simulating digital chips is facing huge pressure from spiralling device gate counts, the simulation of mixed-signal devices has its own special challenges, says Malter, who was in London this week.
“The industry must get out of silo thinking, keeping the digital and analogue elements of the design separate,” said Malter.
“The critical area is the interface between analogue and digital elements. The industry must adopt an approach which simulates the whole chip,” said Malter.
“In a way we are re-learning the chip modelling problem,” said Malter.
“I believe we are moving to higher levels of abstraction, where digital designers will be able to implement and simulate the analogue functions,” said Malter.
Amongst Cadence’s European customers, Malter said it is typical to see mixed-signal chip design projects where the analogue functions are becoming the important element of the design.
“We call these ‘analogue on top’ designs where the analogue guy owns the schematic, this is typical in European companies,” said Malter.
“This is important in Europe, which is leading in mixed-signal design,” said Malter.
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